A graphics processing system includes a graphics processor and a memory for storing data to be used by and generated by the graphics processor. In a first rendering pass, the graphics processor generates an array of graphics data and stores the generated array of graphics data in the memory. The array of graphics data generated in the first rendering pass is used in a subsequent rendering pass. In the first rendering pass, the graphics processor determines one or more regions of the array of graphics data that have a particular characteristic, and generates information indicative of the one or more regions. In the subsequent rendering pass, the graphics processor uses the information indicative of the one or more regions to control the reading of the array of graphics data when it is to be used in the subsequent rendering pass.

Graphics processing systems

A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

Memory management system and method

In one general aspect, a network communication unit is disclosed that includes connection servicing logic that is responsive to transport-layer headers and is operative to service virtual, error-free network connections. A programmable parser is responsive to the connection servicing logic and is operative to parse application-level information received by the connection servicing logic for at least a first of the connections. Also included is application processing logic that is responsive to the parser and operative to operate on information received through at least the first of the connections based on parsing results from the parser.

Object aware transport-layer network processing engine

An apparatus and method is provided for allowing I/O devices to be shared and/or partitioned among a plurality of processing complexes within the load/store fabric of each of the processing complexes without requiring modification to the operating system or driver software of the processing complexes. The apparatus and method includes a switch for selectively coupling each of the processing complexes to one or more shared I/O devices. The apparatus and method further includes placing information within packets transmitted between the switch and the I/O devices to identify which of the processing complexes the packets are associated with. The invention further includes an apparatus and method within the shared I/O devices to allow the shared I/O devices to service each of the processing complexes independently.

Method and apparatus for shared I/O in a load/store fabric

An apparatus and method are provided that enable I/O devices to be shared among multiple operating system domains. The apparatus has a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains through a PCI Express fabric. Each of the first plurality of I/O ports is configured to route PCI Express transactions between said plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint, where the first shared input/output endpoint is configured to request/complete said PCI Express transactions for each of the plurality of operating system domains. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the PCI Express transactions between the first plurality of I/O ports and the second I/O port.

Switching apparatus and method for providing shared i/o within a load-store fabric

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation

Apparatus, system, and method for bus link width optimization

A computer system includes an integrated graphics subsystem and a graphics connector for attaching either an auxiliary graphics subsystem or a loopback card A first bus connection communicates data from the computer system to the integrated graphics subsystem With a loopback card in place, data travels from the integrated graphics subsystem back to the computer system via a second bus connection When the auxiliary graphics subsystem is attached, the integrated graphics subsystem operates in a data forwarding mode Data is communicated to the integrated graphics subsystem via the first bus connection The integrated graphics subsystem then forwards data to the auxiliary graphics subsystem A portion of the second bus connection communicates data from the auxiliary graphics subsystem back to the computer system The auxiliary graphics subsystem communicates display information back to the integrated graphics subsystem, where it is used to control a display device

Point-to-point bus bridging without a bridge controller

A memory system and methods of operating the same that drastically increase the efficiency in memory use and allocation in graphics systems. In a graphics system using a tiled architecture, instead of pre-allocating a fixed amount of memory for each tile, the invention dynamically allocates varying amounts of memory per tile depending on the demand. In one embodiment all or a portion of the available memory is divided into smaller pages that are preferably equal in size. Memory allocation is done by page based on the amount of memory required for a given tile.

Demand-based memory system for graphics applications

A computer graphics system splits vertex data into first and second streams and stores the streams in separate regions of memory. In a specific embodiment, the first stream includes positional data and the second stream includes non-positional color and texture data. A visibility subsystem uses only the first stream to perform visibility processing, thus reducing bandwidth requirement. The rendering system processes data from subsets, identified by the visibility subsystem, of both streams required to render the visible part of a scene.

Data stream splitting and storage in graphics data processing

A graphics processing subsystem uses system memory as its graphics memory for rendering and scanout of images. To prevent deadlock of the data bus, the graphics processing subsystem may use an alternate virtual channel of the data bus to access additional data from system memory needed to complete a write operation of a first data. In communicating with the system memory, a data packet including extended byte enable information allows the graphics processing subsystem to write large quantities of data with arbitrary byte masking to system memory. To leverage the high degree of two-dimensional locality of rendered image data, the graphics processing subsystem arranges image data in a tiled format in system memory. A tile translation unit converts image data virtual addresses to corresponding system memory addresses. The graphics processing subsystem reads image data from system memory and converts it into a display signal.

Oren Rubinstein

Papers

Apparatus, system, and method for bus link width optimization

Point-to-point bus bridging without a bridge controller

Demand-based memory system for graphics applications

Data stream splitting and storage in graphics data processing

GPU rendering to system memory