L
Luca Baldanzi
Researcher at University of Pisa
Publications - 13
Citations - 98
Luca Baldanzi is an academic researcher from University of Pisa. The author has contributed to research in topics: Cryptography & Encryption. The author has an hindex of 3, co-authored 12 publications receiving 34 citations.
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Journal ArticleDOI
Cryptographically Secure Pseudo-Random Number Generator IP-Core Based on SHA2 Algorithm
Luca Baldanzi,Luca Crocetti,Francesco Falaschi,Matteo Bertolucci,Jacopo Belli,Luca Fanucci,Sergio Saponara +6 more
TL;DR: A Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications is presented.
Journal ArticleDOI
Secure Elliptic Curve Crypto-Processor for Real-Time IoT Applications
Stefano Di Matteo,Luca Baldanzi,Luca Crocetti,Pietro Nannipieri,Luca Fanucci,Sergio Saponara +5 more
TL;DR: A modified version of Double-And-Add-Always algorithm for Point Multiplication has been proposed, which allows the execution of Point Addition and Doubling operations concurrently and implements countermeasures against power and timing attacks.
Journal ArticleDOI
True Random Number Generator Based on Fibonacci-Galois Ring Oscillators for FPGA
Pietro Nannipieri,Stefano Di Matteo,Luca Baldanzi,Luca Crocetti,Jacopo Belli,Luca Fanucci,Sergio Saponara +6 more
TL;DR: The work presented herein describes the design and the validation of a digital True Random Number Generator for cryptographically secure applications on Field Programmable Gate Array, derived from the Fibonacci-Galois Ring Oscillator, supporting throughput up to 400 Mbps.
Journal ArticleDOI
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative
Pietro Nannipieri,Matteo Bertolucci,Luca Baldanzi,Luca Crocetti,Stefano Di Matteo,Francesco Falaschi,Luca Fanucci,Sergio Saponara +7 more
TL;DR: One of the main contributions is that this is the first SHA-2 SHA-3 accelerator synthesised on such advanced technology, and demonstrates absolute performances beyond the state-of-the-art and efficiency aligned with it.
Proceedings ArticleDOI
Crypto Accelerators for Power-Efficient and Real-Time on-Chip Implementation of Secure Algorithms
TL;DR: This work provides a comparison among pure software approach (both on 32b and 64b processors) and hardware-based solutions developed for FPGA and ASIC System-on-Chip platforms, for the most common symmetric-key and public-key cryptographic algorithms.