Damascene copper electroplating for on-chip interconnections, a process that we conceived and developed in the early 1990s, makes it possible to fill submicron trenches and vias with copper without creating a void or a seam and has thus proven superior to other technologies of copper deposition. We discuss here the relationship of additives in the plating bath to superfilling, the phenomenon that results in superconformal coverage, and we present a numerical model which accounts for the experimentally observed profile evolution of the plated metal.

Damascene copper electroplating for chip interconnections

A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.

Method of forming a germanium oxynitride film

There is provided a method of forming a layer, comprising depositing a seed layer on the substrate and depositing a bulk layer on the seed layer. Depositing the seed layer comprises supplying a first precursor comprising metal and halogen atoms to the substrate; and supplying a first reactant to the substrate. Depositing the bulk layer comprises supplying a second precursor comprising metal and halogen atoms to the seed layer and supplying a second reactant to the seed layer.

Layer forming method

The method relates to a method of forming an enhanced unexposed photoresist layer from an unexposed photoresist layer on a substrate by increasing the sensitivity of the unexposed photoresist to exposure radiation. The method comprises: providing the substrate with the unexposed photoresist layer in a reaction chamber; providing a first precursor comprising a portion of a photosensitizer sensitive to exposure radiation in the reaction chamber; and, infiltrating the unexposed photoresist layer on the substrate with the first precursor.

Method of forming an enhanced unexposed photoresist layer

A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

Method for selectively depositing a Group IV semiconductor and related semiconductor device structures

Building upon the depth and breadth of Harold Winters's work, this paper pays tribute to his pioneering contribution in the field of plasma etching of metals, and how that knowledge base helps guide the fundamental research in these areas. The fundamental understanding of the plasma–surface interactions during metal etch is key to achieve desirable etch efficacy and selectivity at the atomic scale. This paper presents a generalized methodology, combining thermodynamic assessment and kinetic verification of surface reactions, using copper, magnetic metals, and noble metals as examples, in an effort to demonstrate the applicability of this strategy in tailoring plasma–surface interactions at the atomic scale for a wide range of materials.

https://avs.scitation.org/doi/pdf/10.1116/1.4993602

Luke Minardi

Papers

Review Article: Plasma–surface interactions at the atomic scale for patterning metals