In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed.

Why is nonvolatile ferroelectric memory field-effect transistor still elusive?

(Ba,Sr)TiO3 (BST) thin films grown by chemical vapor deposition and with platinum (Pt) top and bottom electrodes have been characterized with respect to the leakage current as a function of temperature and applied voltage. The data can be interpreted via a thermionic emission model. The Schottky approximation accounts for superohmic behavior at higher fields, but the barrier lowering is stronger than expected from this theory. While the leakage mechanism is comparable to SrTiO3 thin films prepared by chemical solution deposition, the absolute values of the leakage current are significantly lower for the metalorganic chemical vapor deposition (MOCVD) prepared BST film. This is presumably due to a more homogeneous microstructure of the latter and may also be due to different electrode processing. The influence of the film thickness on the leakage in combination with additional findings is used to discuss the field distribution in the films under a dc voltage stress.

Leakage currents in Ba0.7Sr0.3TiO3 thin films for ultrahigh-density dynamic random access memories

https://ir.nctu.edu.tw:443/bitstream/11536/30330/1/000087849500001.pdf

Progress in the developments of (Ba,Sr)TiO3 (BST) thin films for Gigabit era DRAMs

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor, where binary data are stored, and one or two transistors that either allow access to the capacitor or amplify its contents for a read operation. Once a cell is accessed for a read operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper. These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memories share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However, they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density and power consumption.

/pdf/a-survey-of-circuit-innovations-in-ferroelectric-random-5q4bm1uaoc.pdf

A survey of circuit innovations in ferroelectric random-access memories

▪ Abstract We discuss high-dielectric films, in general, oxide ferroelectrics based on simple perovskite structures and related Aurivillius-phase layered structure perovskites employed as thin-film capacitors in dynamic random access memories (DRAMs). Emphasis is on breakdown mechanisms and limits, leakage currents, electrodes and electrode interfaces, scaling to submicron geometries, and deposition techniques.

/pdf/high-dielectric-constant-thin-films-for-dynamic-random-1nwgr1crov.pdf

High-dielectric constant thin films for dynamic random access memories (dram)

We present a study of breakdown fields in BaxSr1−xTiO3 ceramics as functions of thickness, temperature, applied voltage ramp rate, electrode material and cross-sectional area. The data show evidence of Zener-like breakdown mechanisms. The d.c. leakage currents at voltages below breakdown are dominated by tunneling injection and image forces at low voltages (≤3 V), Schottky behavior at intermediate voltages V a (3 V ≤ V a ≤ 6 V; 150 kV/cm ≤ E ≤ 300 kV/cm), and Fowler-Nordheim tunneling at high voltages; it is shown that both the Schottky emission regime and the ultimate breakdown arise from inter-grain effects rather than the BST/electrode interface, in accord with the theory of Neumann and Arlt and of Waser and Klee. In contrast to PbZrxTi1−xO3 (PZT), which displays avalanche breakdown and space-charge limited d.c. leakage currents at normal 5 V silicon IC voltages, BST exhibits Schottky-dominated leakage currents in this 5 V regime, and is dominated by Fowler-Nordheim tunneling in its breakdown ...

Dielectric breakdown in high-ε films for ULSI DRAMs: II. barium-strontium titanate ceramics

One of the most important features for ferroelectric material is fast write at low voltage. This feature is used in a 256 kb nonvolatile memory that operates at 3 V power supply with a read/write time of 100 ns. Active current is 3 mA at 200 ns cycle time at 3 V for battery operation. The cell consists of 1 transistor and 1 capacitor per bit (1T1C) permitting a high level of integration. For low-voltage low-power operation, use is made of a preset reference-cell circuit, wordline boost circuits with a ferroelectric boosting capacitor and a divided-cell plate circuit. >

A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns

We have successfully incorporated the ferroelectric and the high dielectric constant capacitors into integrated circuits. The GaAs MMICs with BST capacitors have been widely used for cellular phones. The BST technology is also applied to a silicon CCD delayline processor for VCRs and camcorders. With respect to the ferroelectric technology with Y1, an experimentally fabricated 256k bit FeRAM has exhibited the remarkable performance of the 100 ns and 3V operation with a 1T/1C cell configuration dedicated for the FeRAM. These integrated ferroelectrics have been achieved by controlling the ferroelectric properties in thin films and incorporating the films into GaAs and silicon devices with outstanding process technology. Furthermore, we refer to the memory cell design technology which enables the FeRAM to work below 1V. Various advantages of low-voltage and high-speed operation inherent in integrated ferroelectrics will be emphasized on the intelligent microelectronics applications toward the next m...

Integration technology of ferroelectrics and the performance of the integrated ferroelectrics

The authors describe the development of a HDTV (high-definition television) CCD (charge-coupled device) imager meeting the requirements for a practical color TV camera implemented with three CCD chips. They present a frame interline transfer CCD image sensor (FIT CCD), with 1258(H)*1035(V) pixels, that uses a poly-Si/Al double-layer transfer gate and p/sup +/-floating-island isolation. The saturation current of the present FIT CCD is 900 nA up to 625 kHz, whereas that of the conventional FIT CCD is fairly poor even at 300 kHz. The high transfer speed results from reduction of gate resistance. The photoconversion characteristics measured at a transfer frequency of 625 kHz show that the sensitivity reaches 50 nA/lx. The measured characteristics of the image sensor meet practical HDTV three-chip camera requirements. >

Frame interline transfer CCD sensor for HDTV camera

This work demonstrates application of ferroelectric technology in the embedded "system-on-chip" area. The focus of this paper is twofold: (1) Optimization of the material properties and cell design to achieve 0.9 V operation with fully-saturated hysteresis loops, and high speed (<100ns); and, (2) Demonstration of the overall "system-on-chip" device architecture and operation using the ferroelectric memory in an embedded environment.

M. Azuma

Papers

Dielectric breakdown in high-ε films for ULSI DRAMs: II. barium-strontium titanate ceramics

A 256 kb nonvolatile ferroelectric memory at 3 V and 100 ns

Integration technology of ferroelectrics and the performance of the integrated ferroelectrics

Frame interline transfer CCD sensor for HDTV camera

A 0.9 V embedded ferroelectric memory for microcontrollers