The latched comparator is a building block of virtually all analog-to-digital converter architectures. It uses a positive feedback mechanism to regenerate the analog input signal into a full-scale digital level. The large voltage variations in the internal nodes are coupled to the input, disturbing the input voltage-this is usually called kickback noise. This brief reviews existing solutions to minimize the kickback noise and proposes two new ones. HSPICE simulations of comparators implemented in a 0.18-/spl mu/m technology demonstrate their effectiveness.

Kickback noise reduction techniques for CMOS latched comparators

The output averaging technique for input amplifiers of a flash ADC has been analyzed mathematically. Expressions have been derived for the reduction of differential nonlinearity, integral nonlinearity, and the necessary number of overrange amplifiers as a function of the output and averaging resistors. This theory is applied to design a 1.6-Gigasample/s 6-b flash ADC in baseline 0.18-/spl mu/m CMOS technology. A distributed track and hold is implemented to achieve a high sample rate. The small input signal is amplified through a cascade of amplifiers and gradually transformed into robust digital signal levels. An averaging termination circuit has been designed to resemble the infinite string of resistors and amplifiers. By applying termination to the averaging network, the amount of overrange amplifiers and, therefore, the power consumption is reduced, while the linearity and speed performance are maintained. The optimum number of parallel pre-amplifiers is derived on the basis of the tradeoff between the amplifier offset and distortion.

A 6-b 1.6-Gsample/s flash ADC in 0.18-/spl mu/m CMOS using averaging termination

We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized in a standard digital 0.13 /spl mu/m CMOS copper technology. Employing capacitive interpolation gives various advantages when designing for low power: no need for a reference resistor ladder, implicit sample-and-hold operation, no edge effects in the interpolation network (as compared to resistive interpolation), and a very low input capacitance of only 400 fF, which leads to an easily drivable analog converter interface. Operating at 1.2 GS/s the ADC achieves an effective resolution bandwidth (ERBW) of 700 MHz, while consuming 160 mW of power. At 600 MS/s we achieve an ERBW of 600 MHz with only 90 mW power consumption, both from a 1.5 V supply. This corresponds to outstanding figure-of-merit numbers (FoM) of 2.2 and 1.5 pJ/convstep, respectively. The module area is 0.12 mm/sup 2/.

A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS

The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm/sup 2/. The ADC is implemented in a 0.25-/spl mu/m pure digital CMOS technology.

A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-/spl mu/m CMOS

In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit.

Speed-power-accuracy tradeoff in high-speed CMOS ADCs

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm/sup 2/ active area, fabricated in 0.35-/spl mu/m CMOS.

M. Choi

Papers

A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS