Many nanometer-scale devices have been proposed and fabricated recently. Several can implement threshold and majority logic efficiently. Research has also begun on design methodologies to keep pace with the development of these devices. Specifically, a threshold logic synthesis tool (TELS) and a majority/minority logic synthesis tool (MALS) have been developed recently. In this paper, we discuss several factorization methods to enhance the efficacy of these two tools significantly. We then augment the design methodology to allow the tools to produce totally self-checking (TSC) circuits which can efficiently implement concurrent error detection. Such circuits can be used to detect run-time errors. Two schemes are used to synthesize TSC circuits - one based on the Berger code and the other on the parity code. We compare and contrast these two schemes. Experimental results establish the effectiveness of the proposed approaches.

Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations

This paper presents a new on-chip time measurement architecture which is based on the time-to-digital conversion (TDC) method that is capable of achieving a timing resolution of tens of femtoseconds without the use of external automatic test equipment (ATE). This is the highest temporal resolution that has been reported to-date and is achieved by the use of the homodyne technique. The proposed architecture has been designed using a 0.12mum CMOS process and simulation results based on foundry transistor models indicates that it is possible to achieve a timing resolution of 40 fs. The time measurement architecture is standalone and occupies a small silicon area, 150mum by 180mum, making it attractive for high resolution on-chip time measurement

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On-Chip Time Measurement Architecture with Femtosecond Timing Resolution

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200x185um) in a 0.12um CMOS Process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.

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On-chip timing measurement architecture with femtosecond resolution

A novel On-chip delay measurement circuit is presented which is suitable for wide applications involving on-chip measurements, monitoring and process compensation. The circuit is based upon multiple characterization units consisting of ring oscillator, latches and counter. The delay unit used in ring oscillator defines the measurement resolution for the characterization unit. Each characterization unit has different delay cell with delay varying by few Pico-seconds (∼1 to 5 picoseconds) with other one, which helps in increasing the resolution. All units give values based on their delay units and collectively all values forms a statistical space whose median gives the pulse width value. In this way, the circuit overcomes the limitations of earlier proposed on-chip measurement systems by offering high accuracy, high resolution and wide range of measurement using very few components. Silicon results on CMOS 40nm technology node for characterization of memory access time based upon proposed system are also presented.

On-chip delay measurement circuit

This work presents a scheme for measuring the timing parameters of a memory's I/O interface — including the setup/hold time and access time. For setup/hold time measurement, we incorporate a procedure that successively adjusts the timing relation between the clock signal and a controllable valid timing window to estimate the setup/hold time. For access time measurement, we propose a circuit that can capture the worst-case access time of an entire Built-In Self-Test (BIST) session as a pulse width, which is then further measured by traditional time-to-digital converter (TDC). Instead of just reporting a digital code, we also propose a calibration scheme so that we can report not just some digital codes, but also their corresponding absolute values. All the design can be constructed by standard cells. We have implemented it in TSMC 0.18nm CMOS process technology. Simulation results show that the setup time error is less than 3%, the hold time error is 7.5%, and the access time error is 4.4%, with about 6.2% area overhead when the memory size is 4096×64.

A fully cell-based design for timing measurement of memory

This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry as presented in M. J. Hsiaoet al. (2004) or circuit duplication based in T. Xia and J. C. Lo (2003). This is achieved by the use of time-to-digital conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering time-to-voltage converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18/spl mu/m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110/spl mu/m /spl times/ 75 /spl mu/m.

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M. Collins

Papers

A programmable time measurement architecture for embedded memory characterization

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution