This paper presents test results and specifications for SJ BISTTM, an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well-known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults of 100 Omega or lower with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock; guaranteed detection is two clock periods. Being able to detect solder joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.

Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJ BIST

Ball Grid Array (BGA) packages have gained wide acceptance for use with FPGAs and the devices are used extensively for digital electronic designs. While these packages provide high interconnect densities, they rely upon an array of closely-spaced solder balls that are subject to cracking, oxidation and eventual failure. These solder joints can contribute to costly intermittencies that drive “No Fault Found” types of situations higher in the service depots. To overcome these intermittency problems, this paper presents a novel, stand-alone Integrated Circuit (IC) to be applied in systems for detection and isolation of intermittency faults in FPGAs. Because the detected faults are isolated before the FPGA begins to exhibit an intermittent failure, this provides more comprehensive approaches to supporting condition-based maintenance (CBM) and Enterprise Health Management (EHM) objectives for critical military/aerospace applications. Categories and Subject Description: 14 [Testing] 14.4 FPGA Testing

Advanced testing and prognostics of Ball Grid Array (BGA) components with a stand-alone monitor IC

Online test method of FPGA solder joint resistance with low power consumption

As FPGA density and overall usage increases, there is a corresponding and growing need to monitor these solder-joint networks. Prior to the introduction of a first sensor, SJ BISTtrade (SJ Built-in-Self-Testtrade), there were no known methods for detecting faults in the solder-joint networks of fully-programmed, operational Field Programmable Gate Arrays (FPGAs). Because SJ BISTtrade requires over 100 mW at 3.3 V to test 8 FPGA pins, we introduce SJ Monitortrade, a lower-power design (less than 5.0 mW) to provide 24x7 health monitoring of selected I/O pins; the complementary form SJ Monitortrade, can be used to monitor the pins of un-powered FPGAs. SJ Monitor is able to detect all solder-joint network faults that last at least as long as 15 nsec and which are at least as low as 100 Omega with no false alarms. This capability allows for detection of faults before they begin to exhibit intermittent failures, which in turn facilitates condition-based maintenance to reduce failures during critical missions.

https://www.microsemi.com/document-portal/doc_view/131711-a-low-power-sensor-design-sj-monitor

A Low-Power Sensor Design, SJ Monitor, for Monitoring 24x7 the Health of BGA Solder Joints

We present a methodology based on the physics of failure, and the sequential probability ratio test, for modeling and monitoring electrical interconnects in health monitoring, and electronic prognostic applications. The resistance behavior of an electrical contact was characterized as a function of temperature. The physics of failure of the contact technology were analysed. A contact resistance model was selected, and its parameters were fitted using the temperature characterization data. The physics of failure model was evaluated with a reliability application (temperature cycle test), and was found to produce estimation errors of < 1 mOmega of during a training period. The temperature and resistance of ten sample contacts were continuously monitored during the temperature cycle test, identifying the maximum temperature and resistances for each cycle. Using the physics of failure model, maximum resistance estimates were generated for each test sample. The residual between the monitored and estimated resistance values was evaluated with the sequential probability ratio test. The method was shown to overcome the issues of traditional threshold-based monitoring approaches, providing accurate resistance estimates, and allowing the detection of abnormal resistance behavior with low false alarm and missed alarm probabilities.

Modeling of IC Socket Contact Resistance for Reliability and Health Monitoring Applications

An update on a method (SJ BISTtrade) to detect intermittencies in Ball Grid Array (BGA) packages is presented, and another method (SJ Monitortrade) is introduced. SJ BISTtrade is primarily firmware embedded in the FPGA application; SJ Monitortrade is hardware on an IC chip. Failure of monitored I/O pins on operational, fully-programmed FPGAs is reported by SJ BIST and SJ Monitor to provide positive indication of damage to one or more I/O solder-joint networks of an FPGA on an electronic digital board. The board can then be replaced before accumulated fatigue damage results in intermittent or long-lasting operational faults.

M.G.P. Adams

Papers

Intermittency detection and mitigation in Ball Grid Array (BGA) packages