In this paper, we present the ReCoBus-builder tool chain that simplifies the generation of dynamically reconfigurable systems to almost a push-button process. The generated systems provide one or more resource areas that will be used by different partially reconfigurable modules at runtime. It is possible to integrate multiple partially reconfigurable modules into the same resource area at the same time and these modules can communicate via a fixed bus infrastructure or dedicated point-to-point links with other parts of the system. This allows building encapsulated modules that will be integrated into the system by linking together bitstreams at runtime. We will demonstrate that bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps, when only small portions of a design are exchanged.

https://www12.informatik.uni-erlangen.de/publications/pub2008/KBT_FPL08.pdf

ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS

Current trends in high performance computing show, that the usage of multiprocessor systems on chip are one approach for the requirements of computing intensive applications. The multiprocessor system on chip (MPSoC) approaches often provide a static and homogeneous infrastructure of networked microprocessor on the chip die. A novel idea in this research area is to introduce the dynamic adaptivity of reconfigurable hardware in order to provide a flexible heterogeneous set of processing elements during run-time. This extension of the MPSoC idea by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized distribution of computing tasks to the adapted processing cells on the architecture related to the changing application requirements. The "computing in time and space"paradigm and the extension with the new degree of freedom for MPSoCs will be presented with the RAMPSoC approach described in this paper.

Runtime adaptive multi-processor system-on-chip: RAMPSoC

A logic chip (1200) comprises a plurality of individually addressable resource blocks (1210, 1220) each of the resource blocks (1210, 1220) comprising logic circuitry (1216, 1226), and a communication bar (1212, 1222) extending across a plurality of the individually addressable resource blocks (1210, 1220). The communication bar comprises a plurality of communication bar segments (1212, 1222) associated with the resource slots (1210, 1220). The communication bar segments (1210, 1222) of the individually addressable resource blocks comprise identical interface locations (1214a, 1214b, 1224a, 1224b) with respect to boundaries of the resource blocks (1210, 1220), such that an input interface location (1214a) of a first resource block (1210) matches an output interface location (1224) of an adjacent second resource block (1220). At least one of the individually addressable resource blocks (1210; 1220) comprises a bypass segment (1212) of the communication bar. At least one of the individually addressable resource blocks (1210, 1220) comprises an access segment (1222) of the communication bar. The access segment (1222) comprises an access structure (1228) inserted between a first communication bar interface location (1224a) and a second communication bar interface location (1224b), to allow for a read access or a write access or a combined read/write access to the communication bar.

Logic chip, logic system and method for designing a logic chip

The research described in this paper shows how the runtime relocation of a reconfigurable component can be obtained using a system component that is able to update the bitstream information, moving the reconfigurable module in the desired position. This scenario defines the so-called partial bitstream relocation activity. This paper proposes a relocation filter that can be implemented both as a hardware and a software component. The former is hosted in the static part of the reconfigurable architecture, while the latter is made to be run on the processor placed on the field-programmable gate array (FPGA). The proposed approach has also been validated over different FPGAs, i.e., Virtex II Pro, Virtex 4, and Virtex 5, proposing a runtime relocation support that can be customized to meet all the different constraints associated with these different target architectures.

Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration

Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has ceased to perform its function, and then the self-organisation is performed again in order to provide that a second cell undertakes the function of the first cell.

Biologically inspired hardware cell architecture

Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures has to be considered. Here, exploitation of real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics. This paper discusses our implemented, synthesized and tested on-demand and partial reconfiguration approaches for fine-grain (Xilinx Virtex FPGAs) data paths. This includes also very new dynamic and partial reconfiguration for 2D placement and routing adaptation for today's fine-grain Xilinx FPGAs.

New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

The progress in hardware technologies for implementing portable, low power and low cost electronic systems for consumer products has been major the last years. The complexity of embedded systems will further increase at a rate which is not met by the development of advanced CAD tools for managing the large design space. This will likely lead to increased design problems regarding system implementation, test and verification. In the next 15-20 years, it is likely that the consumer products are based on computing devices which are grouped together in networks including thousands or even millions of nodes. The /ETHER project deals with managing the complexity of such systems based on emerging technologies for future applications. This paper presents how the design complexity can be managed at the hardware level by integrating self-adaptive characteristics, and how the trade-off in performance and flexibility can be optimized to fulfill all application requirements while reducing the design complexity.

M. Hiibner

Papers

New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits

On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project