Proceedings ArticleDOI
New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits
M. Hiibner,Christian Schuck,M. Kiihnle,Jürgen Becker +3 more
- pp 97-102
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TLDR
In this paper, a real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics.Abstract:
Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while design-time, e.g. for system-on-chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures has to be considered. Here, exploitation of real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics. This paper discusses our implemented, synthesized and tested on-demand and partial reconfiguration approaches for fine-grain (Xilinx Virtex FPGAs) data paths. This includes also very new dynamic and partial reconfiguration for 2D placement and routing adaptation for today's fine-grain Xilinx FPGAs.read more
Citations
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Proceedings ArticleDOI
ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS
TL;DR: The ReCoBus-builder tool chain is presented that simplifies the generation of dynamically reconfigurable systems to almost a push-button process and bitstream linking can further be used to speed up the design process of static only systems by eliminating long synthesis runs or place and route steps.
Proceedings ArticleDOI
Runtime adaptive multi-processor system-on-chip: RAMPSoC
TL;DR: The RAMPSoC approach by introducing run-time reconfiguration delivers a new degree of freedom for system design as well as for the optimized distribution of computing tasks to the adapted processing cells on the architecture related to the changing application requirements.
Patent
Logic chip, logic system and method for designing a logic chip
TL;DR: In this paper, a logic chip (1200) comprises a plurality of individually addressable resource blocks (1210, 1220) each of the resource blocks comprising logic circuitry (1216, 1226), and a communication bar (1212, 1222) extending across a plurality thereof.
Journal ArticleDOI
Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration
TL;DR: This paper proposes a relocation filter that can be implemented both as a hardware and a software component, and can be customized to meet all the different constraints associated with these different target architectures.
Proceedings ArticleDOI
Efficient Reconfigurable On-Chip Buses for FPGAs
TL;DR: This paper presents techniques for generating on-chip buses suitable for dynamically integrating hardware modules into an FPGA-based SoC by partial reconfiguration with minimized latency and area overheads.
References
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Proceedings ArticleDOI
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Proceedings ArticleDOI
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