In the last decade an important shift has taken place in the design of hardware with the advent of smaller and denser integrated circuits and packages. Analysis techniques are required to ensure the proper electrical functioning of this hardware. In this paper we give a coherent survey of the modeling and computer-aided design techniques applicable to solving these problems. Methods are considered for the computation of resistances, capacitances, and inductances. Also, an extensive list of references is given.

Survey of computer-aided electrical analysis of integrated circuit interconnections

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.

A 30-ps Josephson current injection logic (CIL)

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.

Josephson-logic devices and circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed. >

Digital logic circuits

Digital electronics at gigabit-per-second data rates is emerging as a new branch of science and engineering. A particular field of application opens up in advanced radar and sensing systems where large amounts of data have to be dealt with in real time. Analog-to-digital (A/D) converters with microwave sampling rates and multipliers for high-data-yield processing are specifically required subcircuits. In communications, special 1 to 2 Gbit/s systems have been developed, but a further commercial need develops in domestic satellite links and in fiber-optical communications with its potential high bandwidth capabilities. Corresponding gigabit measuring and test instrumentation is required and being implemented. Gigabit circuitry has so far mainly been realized in hybrid-integrated technology. However, the full use of modern technological tools now allows for the fabrication of gigabit monolithic integrated circuits (IC's), with circuits up to 4 Gbit/s implemented. In circuit design, specific problems must be solved which are due to the involved wide bandwidths at microwave spectral frequencies. High packing density is required for low interconnection delay, but power dissipation leads to limitations. Gigabit electronics is based on devices with switching speeds in the range of a few hundred picoseconds and lower. Besides pin diodes and Schottky diodes, transistors are investigated at first. While the Si bi-polar has been improved, it is the GaAs MESFET and the GaAs junction FET which excel in speed, with LSI capabilities. Very recently, a considerable speed improvement was reported for Si n-MOSFET's. Unique properties for gigabit logic are shown by transferred-electron devices. However, the lead with regard to high speed and low power have Josephson junctions of the in-line junction and of the interferometer types. The present phase of rapid gigabit IC development, with expected LSI circuits in the 2 to 5 Gbit/s range and MSI circuits up to 15 Gbit/s, will stimulate further applications.

Gigabit electronics&#8212;A review

Josephson interferometer logic gates have been operated experimentally with an average logic delay of 55 ps per stage. The gates operated with an AC power supply in a latching mode with a reset capability consistent with a machine cycle time less than 5 ns. OR, AND, and INVERT functions and fanout capability were demonstrated. Dissipation per gate was about 2.0 /spl mu/W.

M. Klein

Papers

Sub-100 ps experimental Josephson interferometer logic gates