Digital technology works so well because at the heart of digital representation, there are only a few basic components. Nowadays, these basic components usually are binary digits, bits for short, called binary because they are designed to stand for only two different values, conveniently called zero and one. A stored or transmitted bit's state can deteriorate quite badly before a processing device will be mistaken in deciding which of the two possible values is the original.

Binary Arithmetic

The Internet of things (IoT) applications are becoming one of the emerging smart grid enabling technologies. Smart home appliances are one the beneficiary of such applications. Machine-to-Machine and Man-to-Machine are the basic IoT communication platforms that enable home appliances to communicate with each other to be more efficiently operated. In a recent search for the IoT communication protocols that are utilized in smart home appliances, there was no inclusive reference that contains and describes the smart home area networks and guides the research and development (R&D) professionals to select the suitable protocol for an application. This paper presents a comprehensive review of the home area network (HAN) communication protocols that are used to enable bidirectional communication between the home owners, utilities and smart home appliances. The paper presents the most utilized HANs wired and wireless communication protocols and discusses their characteristics, advantages and disadvantages.

/pdf/smart-home-area-networks-protocols-within-the-smart-grid-17b4rfoati.pdf

Smart Home Area Networks Protocols within the Smart Grid Context

https://hal.archives-ouvertes.fr/hal-02182827/document

Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses

Proceedings of the IEEE International Symposium on Industrial Electronics

Frequency synthesizers: Theory and design

I2C and SPI are the most commonly used serial protocols for both inter-chip and intra-chip low/medium bandwidth data-transfers. This paper contrasts and compares physical implementation aspects of the two protocols through a number of recent Xilinx?s FPGA families, showing up which protocol features are responsible of substantial area overhead. This valuable information helps designers to make careful and tightly tailored architecture decisions. For a comprehensive comparative study, both protocols are implemented as general purpose IP solutions, incorporating all necessary features required by modern ASIC/SoC applications according to a recent market investigation of an important number of commercial I2C and SPI devices. The RTL code is technology independent, inducing around 25% area overhead for I2C over SPI, and almost the same delays for both designs.

FPGA implementation of I 2 C & SPI protocols: A comparative study

SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers.

Design and test of general-purpose SPI Master/Slave IPs on OPB bus

In a previous brief, we proposed a new sublinear-runtime recoding heuristic for the multiplication by a constant, accompanied by its upper bound complexity. In this brief, further results are provided, namely, the analytic expressions of the average number of additions and the maximum adder depth. Improvements to the proposed heuristic are considered as well, using a redundant recoding followed by a common-digit-elimination step.

Radix-2 r Arithmetic for Multiplication by a Constant: Further Results and Improvements

ASIC or FPGA implementation of a finite word-length PID controller requires a double expertise: in control system and hardware design. In this paper, we only focus on the hardware side of the problem. Weshow how to design configurable fixed-point PIDs to satisfy applications requiring minimal power consumption, or high control-rate, or both together. As multiply operation is the engine of PID, we experienced three algorithms: Booth, modified Booth, and a new recursive multi-bit multiplication algorithm. This later enables the construction of finely grained PID structures with bit-level and unit-time precision. Such a feature permits to tailor the PID to the desired performance and power budget. All PIDs are implemented at register-transfer-level (RTL) level as technology-independent reusable IP-cores. They are reconfigurable according to two compile-time constants: set-point word-length and latency. To make PID design easily reproducible, all necessary implementation details are provided and discussed.

/pdf/design-of-high-speed-and-low-power-finite-word-length-pid-2sz2wg42fu.pdf

Design of high-speed and low-power finite-word-length PID controllers

In a recent work, we have introduced a new multiple constant multiplication (MCM) algorithm, denoted as RADIX-2 r . The latter exhibits the best results in speed and power, comparatively with the most prominent algorithms. In this paper, the area aspect of RADIX-2 r is more specially investigated. RADIX-2 r is confronted to area efficient algorithms, notably to the cumulative benefit heuristic (Hcub) known for its lowest adder-cost. A number of benchmark FIR filters of growing complexity served for comparison. The results showed that RADIX-2 r is better than Hcub in area, especially for high order filters where the saving ranges from 1.50% up to 3.46%. This advantage is analytically proved and experimentally confirmed using a 65nm CMOS technology. Area efficiency is achieved along with important savings in speed and power, ranging from 6.37% up to 38.01% and from 9.30% up to 25.85%, respectively. When MCM blocks are implemented alone, the savings are higher: 10.18%, 47.24%, and 41.27% in area, speed, and power, respectively. Most importantly, we prove that MCM heuristics using similar addition pattern (A-operation with the same shift spans) as Hcub yield excessive bit-adder overhead in MCM problems of high complexity. As such, they are not competitive to RADIX-2 r in high order filters.

https://ietresearch.onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2017.0058

M. L. Berrandjia

Papers

FPGA implementation of I 2 C & SPI protocols: A comparative study

Design and test of general-purpose SPI Master/Slave IPs on OPB bus

Radix-2 r Arithmetic for Multiplication by a Constant: Further Results and Improvements

Design of high-speed and low-power finite-word-length PID controllers

Design of high-speed, low-power, and area-efficient FIR filters