This letter presents a spin-orbit torque magnetic random access memory (SOT-MRAM) for high-density, reliable, and energy-efficient on-chip memory application. Unlike the conventional SOT-MRAM requiring two access transistors, the proposed MRAM uses only one access transistor along with a Schottky diode in order to achieve high integration density while maintaining the advantages of SOT-MRAM, such as low write energy and enhanced reliability of magnetic tunnel junction. The Schottky diode is forward-biased during read, whereas it is reverse-biased during write to prevent sneak current paths. Our simulation results show that the proposed MRAM can achieve 30% and 50% reduction in bit-cell area in comparison to conventional spin-transfer torque MRAM (STT-MRAM) and SOT-MRAM, respectively, and $\sim 2.5\times $ improvement in write power compared with the STT-MRAM.

Area-Efficient SOT-MRAM With a Schottky Diode

Crossbar array of selector-less TaOx/TiO2 bilayer RRAM

We propose a multibit-per-cell architecture for spin-orbit torque magnetic random access memory (MBC SOT-MRAM) for high-density memory applications. By employing two diode-based magnetic tunnel junctions with a shared common heavy metal electrode, our architecture requires only one transistor to access two bits. This leads to at least double the density compared to existing MRAM designs. Based on the high-density MRAM process design rules, a two-bit cell area of 8 F2 may be realized, which may result in an effective one-bit area of 4 F2. In addition, our design attains similar energy consumption compared to conventional SOT-MRAM.

Area-Efficient Multibit-per-Cell Architecture for Spin-Orbit-Torque Magnetic Random-Access Memory With Dedicated Diodes

This paper proposes a diode-based multi-level cell spin–orbit torque magnetic random-access memory (SOT-MRAM) for high density memory applications. By stacking a shared diode over two in-parallel magnetic tunnel junctions (MTJs) that share a common heavy metal electrode, our proposed cell requires only one silicon-based transistor to access 2 bits. Having just one transistor to access 2 bits results in at least $2\times $ higher density when compared to various designs in the literature. Moreover, utilizing a high-density MRAM process, a $4F^{2}$ effective 1 bit area can be achieved. Furthermore, our proposed design maintains the high energy efficiency of the conventional SOT-MRAM. In addition, an improvement in figure of merit of at least 30% defined as energy area product is obtained compared to various designs. This paper also discusses the essential requirements to realize our proposed SOT-MRAM, such as the realization of diode MTJ stack and SOT-MTJs, with different critical currents and electrical resistances.

Area Efficient Shared Diode Multi-Level Cell SOT-MRAM

A physical transient memristor synapse with self-rectifying and analogue switching behaviors based on Mo/MgO/AZO (Al2O3 2 wt %, ZnO 98 wt %)/W is presented. By modulating thickness of MgO layer, the device with 5 nm MgO insulator layer shows stable resistive switching memory with a rectification ratio up to 102, and precise tuning synaptic functions. Meanwhile, the formation of Schottky barrier and oxygen vacancy conductive filament is proposed to further explain self-rectifying and analogue switching behaviors. Additionally, the electrical characteristics of the Mo/MgO/AZO/W devices degraded after being immersed in deionized water (DI) for 3 min, which demonstrated the physically transient features successfully. The physical transient self-rectifying memristors have great potential for applications in secure neuromorphic computing systems, and bio-integrated electronics.

A Physically Transient Self-Rectifying and Analogue Switching Memristor Synapse

Different from conventional unipolar type 1D1R RRAM devices, in this paper, a bipolar type 1D1R RRAM device structure is firstly proposed and successfully demonstrated by the combined TiOx-based Schottky diode and Cu/HfO2/Pt bipolar RRAM cell. Reliable and uniform self-compliance resistive switching characteristics are obtained by imposing current compliance using the reverse bias current of the TiOx-based Schottky diode. Experiment results show that the novel self-compliance bipolar 1D1R device has high potentiality for high-density integrated nonvolatile memory application.

M. Liu

Papers

Novel self-compliance Bipolar 1D1R memory device for high-density RRAM application