FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

The widespread use of the IEEE 1149.1 standard test access port as the interface for not only boundary scan but also for access to device-internal test features has led to a highly useful but highly fragmented opportunity for the test community. The need for a standard description of internal test features and protocols is elucidated, and the framework for the extension of the boundary scan standards as launched by the ad hoc IJTAG working group is described

/pdf/ijtag-internal-jtag-a-step-toward-a-dft-standard-432x036ki5.pdf

IJTAG (internal JTAG): a step toward a DFT standard

Embedded test of memory and random logic can enable very low cost ATE to test large, high speed ICs because high quality at-speed tests can be generated onchip. However, it is also necessary to test the DC and AC parameters of the input/output (I/O) circuitry. This paper describes how most I/O pin characteristics can be tested cost-effectively with a variety of novel techniques that exploit the 1149.1 and 1149.4 test standards. The techniques measure VOL/IOL, VOH/IOH, VIH, and VIL at DC, perform at-speed I/O wrap, and test on-chip power rail impedance, all via minimum pin-count (MPC) access. The 1149.4 bus is also suitable, of course, for testing mixed-signal functions. The paper then discusses costs and benefits of MPC testing of high pin-count ICs on a low cost tester to show that testing costs can be reduced to insignificance.

Complete, contactless I/O testing reaching the boundary in minimizing digital IC testing cost

Characterizing board test coverage as a percentage of devices or nodes having tests does not accurately portray coverage, especially in a limited access testing environment that today includes a variety of diverse testing approaches from visual and penetrative inspection to classical in-circuit test. A better depiction of test coverage is achieved by developing a list of potential defects referred to as the defect universe, where the capabilities of the chosen test strategy are not considered in development of this defect list. Coverage is measured by grading the capabilities of each test process against the defect universe. The defect universe is defined to be meaningful to the bulk of the electronics industry and to provide a consistent framework for coverage metrics and comparisons.

Test coverage: what does it mean when a board test passes?

We present cost and benefit models and analyze the economics effects of built-in self-test (BIST) for logic and memory cores. In our cost and benefit models for BIST, we take into consideration the design verification time and test development time associated with testability. Experimental results for logic BIST and memory BIST examples show that a threshold volume exists when BIST is profitable for the logic core under consideration - it is not recommended for a higher volume. However, BIST is a good choice for memory cores in general.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/2000/date00/pdffiles/10d_1.pdf

Cost and benefit models for logic and memory BIST

An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate component functional defect rate and test coverage. A new yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given.

Defects, fault coverage, yield and cost, in board manufacturing

In this paper we discuss board test coverage of opens for power pins of large ASICs soldered to electronic boards. Multiple power pin connections cannot be tested by typical electrical testing techniques because they are connected in parallel between the package and the board. We present in this paper an estimate of the probability of these power pin opens, outline the impact of the lack of test coverage in system performance, and offer possible solutions to the problem,.

Opens board test coverage: when is 99% really 40%?

A board and multi-chip module (MCM) manufacturing test simulator (MTSIM) is described, MTSIM is a concurrent engineering tool used to simulate the manufacturing test and repair aspects of boards and MCMs from design concept through manufacturing release. MTSIM helps designers select assembly process, specify, design for test (DFT) features, select board test coverage specify ASIC defect level goals, establish product feasibility, and predict manufacturing quality and cost goals. MTSIM was implemented in the Mentor Graphics Falcon framework at Colorado State University (CSU) and validated with high performance assemblies at Hewlett-Packard (HP). MTSIM is a step towards the simulation of the whole board/MCM assembly factory.

Manufacturing test simulator: a concurrent engineering tool for boards and MCMs

This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets.

ASIC yield estimation at early design cycle

The authors discuss the status and celebrate the success of IEEE Std 1149.1, hoping to motivate discussion and action that will encourage further development of boundary scan-based testing. They offer the insight of experienced implementers of the standard working in competitive business environments. >

M.M.V. Tegethoff

Papers

Defects, fault coverage, yield and cost, in board manufacturing

Opens board test coverage: when is 99% really 40%?

Manufacturing test simulator: a concurrent engineering tool for boards and MCMs

ASIC yield estimation at early design cycle

IEEE Std 1149.1: where are we? where from here?