In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.

EMC-aware design on a microcontroller for automotive applications

In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, introducing new challenges to ensure the power integrity (PI) of the electronic systems, and increasing the electromagnetic interference (EMI). The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions and modeling techniques to assess and guarantee PI and electromagnetic compatibility (EMC) across the overall system that comprises the chip, package, and printed circuit board (PCB). Hence, PI and EMC/EMI are rapidly becoming a major concern for high-speed circuit, package, and board designers. In this work we investigate the impact of the chip power rail noise on system PI and EMI, and we show that by reducing the power rail noise thus assuring the system PI, it is possible to significantly reduce the electromagnetic (EM) conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and PCB designers to predict the power integrity and the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.

Advanced modeling techniques for system-level power integrity and EMC analysis

This paper presents a compact model for on-chip decoupling capacitors (decaps) including gate-oxide leakage. The model makes use of only four parameters, namely, channel resistance, gate-oxide capacitance, and two parameters to quantify gate-oxide leakage, to predict the static and dynamic response of decaps. Quality indices have been defined to enable development of decap design guidelines and evaluation of performance of such capacitors. The model shows how the gate leakage and longer channel lengths severely affect the performance of on-chip decaps for both low and high frequencies. The model also shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. Application of the model uncovers tradeoffs for thin- and thick-oxide capacitors in an available 90-nm CMOS technology. For a general-purpose technology, a reference capacitance value has been realized using decaps with a discrete width and length. Our model predicts that thick-oxide n-channel (p-channel) capacitors require /spl sim/3.37x (/spl sim/3.31x) more silicon area and /spl sim/1.70x (/spl sim/1.17x) degraded time response as compared to their thin-oxide versions. The time response is even more degraded (/spl prop/L/sup 2/) when longer channel decaps are used. This paper contributes by defining performance benchmarks for decaps.

A high-frequency nonquasi-static analytical model including gate leakage effects for on-chip decoupling capacitors

This work presents a model for on-chip decoupling capacitors (decaps) including gate tunnelling current. The model shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. It also shows how the gate leakage reduces the effectiveness of such decaps for both, low and high frequencies.

A model for on-chip decoupling capacitor effectiveness including gate leakage effects

Le present travail de these porte sur l’etude, la conception et la demonstration d'emetteurs entierement numeriques, ciblant des standards de communication avances pour les applications mobiles dans le cadre de l’Internet des Objets (IoT). Les innovations cles sont le modulateur Delta-Sigma (DSM) entrelace et un amplificateur de puissance a reponse impulsionnelle finie (FIR-PA) base sur une structure efficace a capacites commutees (SC). Le block FIR-PA utilise uniquement des inverseurs CMOS et des condensateurs dans une configuration SC, ce qui est entierement compatible avec les nœuds technologiques CMOS avances. Le prototype est implemente dans une technologie 28nm FD-SOI CMOS avec 10 couches metalliques et un controle ameliore de la tension du substrat. L'emetteur RF numerique atteint un nombre de bits effectif de 13.5 dans la bande de signal utile et est compatible avec le standard LTE 900 MHz. Le circuit consomme 35 mW a une puissance de sortie maximale de 2.9 dBm et une alimentation de 1 V. Par rapport a l'etat de l'art, a des niveaux de puissance de sortie similaires, le FIR-PA consomme 7 fois moins qu'un DAC 10-bit integrant des modulateurs delta-sigma et 25% moins qu’un DAC resistif 12-bit. La surface active totale est de 0.047 mm2, soit 4 fois moins que le plus petit circuit publie precedemment. Par consequent, ce travail se distingue par une faible consommation d'energie grâce a la l’architecture 1-bit combinee au filtrage de bande et par la surface reduite obtenue par l’integration efficace des cellules du FIR-PA. Il demontre la transition de l’emetteur analogique traditionnel a l’emetteur numerique integre ciblant l'avenir des applications mobiles.

Transmetteurs radiofréquences numériques fortement parallélisés avec amplificateur de puissance commuté et filtre de bande embarqués en technologie 28nm FD-SOI CMOS

High-speed digital circuits require increasing amounts of on-chip decoupling capacitors (decaps) to preserve power integrity. Therefore, proper modelling and analysis of the dynamic response of such decaps in the high frequency range is needed. This paper shows that, in that range, lumped decap models fail and have to be substituted by distributed models. A derivation of such distributed model based on physical grounds is presented and compared with SPICE non-quasi static MOS models.

M. Meijer

Papers

Modelling the dynamic response of on-chip decoupling capacitors