Circuit design techniques are described for switched-capacitor filters, modulators, rectifiers, detectors, and oscillators. The applications of these circuits in telecommunications, speech processing, and other signal-processing systems are also briefly discussed.

Switched-capacitor circuit design

An improved auto-zeroing feedback control circuit (FIG. 1) is disclosed to compensate for DC offset voltages in signal coding applications. The feedback control circuit for a signal limiter (120) includes a digital integrator (130) which oversamples the limited output (125). When the accumulated sample count overflows, an analog integrator (140) is enabled, and a small quantity of charge is delivered to the integrating capacitor. The analog integrator output signal (145) is then attenuated (150) and used to adjust the bias for the limiter (120). This improved auto-zeroing technique eliminates the requirement of a large external auto-zero capacitor, and permits the signal coder to be fully integrated on-chip.

Auto-zeroing circuit for offset cancellation

Practical techniques are given for reducing the number of operational amplifiers (op-amps) in switched capacitor filters. Op-amp count is typically reduced to one op-amp per pole pair, while maintaining the insensitivity to top and bottom plate parasitics heretofore associated with one-op-amp-per-pole structures. These techniques are used to develop a parasitic insensitive single amplifier resonator and a general single amplifier biquad. Next, complete design procedures are given for these circuits. Finally, the same methods are applied to leapfrog structures, where similar op-amp savings are demonstrated.

http://ieeexplore.ieee.org/iel7/6731005/6779756/06779758.pdf

Parasitic insensitive, biphase switched capacitor filters realized with one operational amplifier per pole pair

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-μm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5–0.2 μm scaled CMOS devices.

A concept of analog-digital merged circuit architecture for future VLSI's

A high-voltage BORSHT LSI family for an all solid-state subscriber line interface circuit in a digital local switching system has been developed. The family consists of a 320 V dielectrically isolated RTLSI, a 60 V bipolar BSH-LSI, and a CMOS control LSI. Ringing, reverse, and network-test functions were implemented in the RT-LSI chip using a high-voltage current-controlled p-n-p-n-switch integration technology. Battery feed, supervision, and hybrid functions have been integrated into the BSH-LSI chip using a high-precision analog bipolar process technology. The CMOS logic LSI performs a digital interface function with the PCM highway, as well as a control function for the other LSIs. Using this BORSHT LSI family along with a codec, it has become possible to make a low-cost and small-size subscriber line interface circuit for central office use.

High-voltage subscriber line interface LSIs

A single-chip CMOS codec with filters has been developed using charge redistribution and switched-capacitor techniques. Its features are ~30 mm/SUP 2/ small chip area, 35 mW low power dissipation, and small 16 pin package. These are achieved with novel analog circuit techniques for A/D and D/A conversions and clock generation. Measured transmission characteristics meet the system requirements.

M. Nakajima

Papers

A single-chip CMOS CODEC with switched-capacitor filters