A fractional delay filter is a device for bandlimited interpolation between samples. It finds applications in numerous fields of signal processing, including communications, array processing, speech processing, and music technology. We present a comprehensive review of FIR and allpass filter design techniques for bandlimited approximation of a fractional digital delay. Emphasis is on simple and efficient methods that are well suited for fast coefficient update or continuous control of the delay value. Various new approaches are proposed and several examples are provided to illustrate the performance of the methods. We also discuss the implementation complexity of the algorithms. We focus on four applications where fractional delay filters are needed: synchronization of digital modems, incommensurate sampling rate conversion, high-resolution pitch prediction, and sound synthesis of musical instruments.

Splitting the unit delay [FIR/all pass filters design]

Timing adjustment in a digital modem must be performed by interpolation if sampling is not synchronized to the data symbols. The author describes the fundamental equation for interpolation, proposes a method for control, and outlines the signal-processing characteristics appropriate to an interpolator. A review of previous results and a tutorial exposition of the subject are given, along with new results. >

Interpolation in digital modems. I. Fundamentals

DVB-S2 is the second-generation specification for satellite broad-band applications, developed by the Digital Video Broadcasting (DVB) Project in 2003. The system is structured as a toolkit to allow the implementation of the following satellite applications: TV and sound broadcasting, interactivity (i.e., Internet access), and professional services, such as TV contribution links and digital satellite news gathering. It has been specified around three concepts: best transmission performance approaching the Shannon limit, total flexibility, and reasonable receiver complexity. Channel coding and modulation are based on more recent developments by the scientific community: low density parity check codes are adopted, combined with QPSK, 8PSK, 16APSK, and 32APSK modulations for the system to work properly on the nonlinear satellite channel. The framing structure allows for maximum flexibility in a versatile system and also synchronization in worst case configurations (low signal-to-noise ratios). Adaptive coding and modulation, when used in one-to-one links, then allows optimization of the transmission parameters for each individual user,dependant on path conditions. Backward-compatible modes are also available,allowing existing DVB-S integrated receivers-decoders to continue working during the transitional period. The paper provides a tutorial overview of the DVB-S2 system, describing its main features and performance in various scenarios and applications.

/pdf/dvb-s2-the-second-generation-standard-for-satellite-broad-1hexqkf3ux.pdf

DVB-S2: The Second Generation Standard for Satellite Broad-Band Services

A method for ongoing power control for a communication station with a multiple antenna array, the power control using a method for signal quality estimation applicable for angle modulated signals. One aspect of the ongoing power control method is applicable for the uplink and includes separating the joint determination of a receive weight vector and ongoing power control into a receive weight vector determining part and a separate transmit power adjustment part. In one embodiment, the ongoing power control method for the downlink includes separating the joint determination of a receive weight vector and ongoing power control into a receive weight vector determining part and a separate transmit power adjustment part. The method starts with one part, for example transmit power assignment. Receive weight vector determination is carried out with this assigned transmit power, and the new weights used. An estimate of the resulting received signal quality is obtained and used for new ongoing power adjustment. Another aspect is applicable for the downlink and includes one aspect of the ongoing power control method is applicable for the uplink and includes separating the determination of a complete transmit weight vector including the vector of relative transmit weights and the scaling to use with the relative transmit weights into a part for determining a set of relative transmit weights and a separate transmit power adjustment part that determines the scaling factor.

Power control with signal quality estimation for smart antenna communication systems

Relying on a kurtosis-type criterion, we develop a low-complexity blind carrier frequency offset (CFO) estimator for orthogonal frequency-division multiplexing (OFDM) systems. We demonstrate analytically how identifiability and performance of this blind CFO estimator depend on the channel's frequency selectivity and the input distribution. We show that this approach can be applied to blind CFO estimation in multi-input multi-output and multiuser OFDM systems. The issues of channel nulls, multiuser interference, and effects of multiple antennas are addressed analytically, and tested via simulations.

https://www.dtc.umn.edu/s/resources/tcom05jan-bcfo.pdf

Blind carrier frequency offset estimation in SISO, MIMO, and multiuser OFDM systems

The digital realization of timing recovery circuits for digital data transmission is considered. A digital algorithm is proposed that can be implemented very efficiently even at high data rates. The resulting timing jitter has been computed and verified by simulations. In contrast to other known algorithms, the one presented here allows free-running sampling oscillators and a novel planar filtering method that prevents synchronization hangups. >

Digital filter and square timing recovery

Using the maximum-likelihood approach, algorithms for detection and synchronization are derived that are well suited for VLSI implementation. Special emphasis is placed on an all-digital implementation where carrier and clock synchronization do not require a feedback of signals to the analog part, which simplifies the analog front-end design (mixing oscillator and A/D converter sampling clock run at fixed frequency). An important advantage of the proposed algorithms is that a high clock rate is not required; only two-four times the symbol rate is needed, depending on amplitude quantization. Implementation aspects, e.g. architecture, and quantization, are considered. A prototype is described which was implemented to prove the feasibility of the concept and to evaluate the performance under practical conditions. >

M. Oerder

Papers

Digital filter and square timing recovery

An all digital receiver architecture for bandwidth efficient transmission at high data rates