This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey

This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time ΔΣ loop. Using only a first order loop filter, the proposed ΔΣ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

A 4 GHz third-order continuous-time ΔΣ ADC is presented with a loop filter topology that absorbs the pole caused by the input capacitance of its 4-bit quantizer and also compensates for the excess delay caused by the quantizer's latency. The ADC was implemented in 45 nm-LP CMOS and achieves 70 dB DR and -74 dBFS THD in a 125 MHz BW, while dissipating 260 mW from 1.1/1.8 V supply. The ADC occupies 0.9 mm2 including the modulator, clock circuitry and decimation filter.

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A 4 GHz Continuous-Time $\Delta\Sigma$ ADC With 70 dB DR and $-$ 74 dBFS THD in 125 MHz BW

Integrators are key building blocks in many analog signal processing circuits and systems. The DC gain of conventional opamp-RC or Gm- C integrators is severely limited by the gain of operational transconductance amplifier (OTA) used to implement them. Process scaling reduces transistor output resistance, which further exacerbates this issue. We propose applying ring oscillator integrators (ROIs) in the design of high order analog filters. ROIs implemented with simple CMOS inverters achieve infinite DC gain at low supply voltages independent of transistor non-idealities and imperfections such as finite output impedance. Consequently, ROIs scale more effectively into newer processes. A prototype fourth order filter designed using the ROIs was fabricated in 90 nm CMOS and occupies an area of 0.29 mm2. Operating with a 0.55 V supply, the filter consumes 2.9 mW power and achieves bandwidth of 7 MHz, SNR of 61.4 dB, SFDR of 67.6 dB and THD of 60.1 dB. The measured IM3 obtained by feeding two tones at 1 MHz and 2 MHz is 63.4 dB.

Analog Filter Design Using Ring Oscillator Integrators

This paper presents a digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear tuning characteristics is eliminated by introducing an inverse voltage-to-frequency transfer function in the signal path. The proposed calibration unit runs in the background and detects the inverse transfer function using a highly digital frequency locked loop. Like many other VCO-based ADCs, the proposed technique does not require analog building blocks such as operational amplifiers, multi-bit feed-back DACs etc., and retains the scaling friendly properties. Implemented in a 90 nm CMOS process, the on-chip calibration improves SNDR of an open-loop VCO-based ADC from 46 dB to more than 73 dB in 5 MHz signal bandwidth while consuming 4.1 mW power. The ADC achieves a figure-of-merit of 91-112 fJ/conv-step for different input frequencies.

A Deterministic Digital Background Calibration Technique for VCO-Based ADCs

The use of a VCO-based integrator and quantizer within a continuous-time (CT) ΔΣ analog-to-digital converter (ADC) structure is explored, and a custom prototype in a 0.13 μm CMOS with a measured performance of 81.2/78.1 dB SNR/SNDR over a 20 MHz bandwidth while consuming 87 mW from a 1.5 V supply and occupying an active area of 0.45 mm2 demonstrated. A key innovation is the explicit use of the oscillator's output phase to avoid the signal distortion that had severely limited the performance of earlier VCO-based ADCs, which had made use of its output frequency only. The proposed VCO-based integrator and quantizer structure enables fourth-order noise shaping with only three opamp-based integrators.

M. Park

Papers

A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time $\Delta\Sigma$ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 $\mu$ m CMOS