Image binarization algorithms in document image analysis divide pixel values into two groups, including white as background and black as foreground. Among others, the local contrast and mean (LCM)‐based thresholding algorithm offers excellent performance in processing degraded documents. This algorithm, however, is susceptible to noise and requires significant hardware resources. In this paper, an energy‐efficient and fault‐tolerant architecture is proposed for implementing the LCM algorithm in stochastic computing (SC). Leveraging correlated input bitstreams, this architecture saves energy and improves the fault tolerance of the implementation. Experimental results show that the proposed LCM stochastic architecture significantly outperforms the stochastic implementation of the Sauvola algorithm in terms of both binarization accuracy and hardware overhead and energy consumption. Even using 16‐bit streams, the proposed circuit produces an error rate lower than 5%. The stochastic implementation of the LCM algorithm using a 16‐bit length FSM‐based LD sequence is 22 times less in area, 26 times less in total power, 28 times less in energy consumption and more fault‐tolerant than the conventional 8‐bit bit‐width weighted binary with the same frequency constraints.

A stochastic computing architecture for local contrast and mean image thresholding algorithm

The hardware implementation of error-tolerant adders using the paradigm of approximate computing has considerably influenced the performance metrics, especially in applications that can compromise accuracy. The foundation for approximate processing is the inclusion of errors in the design to enhance the effectiveness and reduce the complexity. This work presents three base adders using the novel concept of error tolerance in digital VLSI design. The research is extended to construct nine variants of power and delay-efficient 16 and 32-bit error-tolerant carry select adders (CSLA). To attain optimization in power and delay, conventional CSLA is refined by substituting ripple carry adders (RCA) with the newly proposed selector unit to minimize the switching activity. The research work includes the power, area, and delay estimates of the design from synthesis using the gpdk-90 nm and gpdk-45 nm standard cell libraries. The proposed adders exhibit reduced delay, power dissipation, area, power delay product (PDP), energy delay product (EDP), and area delay product (ADP) compared to the existing approximate adders. The proposed adder is used in an image blending application. There is a significant improvement in the peak-signal-to-noise ratio (PSNR) in the blended image compared to the standard designs.

https://www.mdpi.com/2079-9292/11/15/2461/pdf?version=1659921835

Performance Metric Evaluation of Error-Tolerant Adders for 2D Image Blending

Quality of real time multimedia images mostly depends on the input, i.e. size of camera sensor, pixel density, quality of lens, etc. therefore the output sometimes contains unsolvable images issues and requires image processing. Approximate computing (AC) has emerged as innovative method for image processing along with the advantages of lower power and high accuracy. In this paper, a review of AC application in image processing is done and a bit truncated Pseudo-8T Static Random Access Memory (BT-PSRAM) is proposed. It is implemented on 32nm CMOS technology node for compressed multimedia applications, and gives encouraging result with low power and energy consumption. Size of Pseudo-8T SRAM has been reduced using 2-bit truncation technique. 

Review of Approximate Computing in Image Processing Applications

The ever-expanding need for low-power devices can be approached by implementing approximate computing methods. A restrictive energy budget is met by dropping the concept of fully exact or entirely deterministic computations. We propose a methodology to trade off accuracy with run-time power consumption through Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs). Optimization is done by switching between predefined design configurations and combining exact and approximate versions of the most power-consuming circuit blocks. We designed a dynamic reconfiguration manager to select and configure the FPGA with the appropriate partial bitstream. The reconfiguration is executed automatically at run time according to the system power state and the accuracy requirement of the running application. The experimental results show that the proposed mechanism can achieve between 10% and 58% power reduction with a maximum error of 0.35 and an average error range of 0.1 beside negligible reconfiguration energy cost. 

Run Time Power and Accuracy Management with Approximate Circuits

The main emphasis of fault-tolerant adders is to minimize the performance metrics area, power and delay. Error resilient applications like Image processing, multimedia, and Internet of Things (IoT) accept degradation in the results providing a wide range of prospects for approximate adder’s optimization. Three designs of fault-tolerant adders Selector Based Fault-Tolerant Adder-I (SBFTA-I), Selector Based Fault- Tolerant Adder-II (SBFTA-II) and Optimized Fault-Tolerant Adder (OFTA) are proposed and implemented in this work with reduced switching activity and gate count. The proposed fault tolerant adders are further used in the design of 16-bit adders, where the upper 8-bits are realized using actual adders, and the lower 8 bits are implemented using the three proposed fault tolerant adder designs. The proposed fault-tolerant and existing approximate adders are synthesized in an electronic design automation (EDA) Tool using a 90 nm technology library. The proposed adder designs showed significantly improved performance metrics compared to the conventional techniques

M. Priyadharshni

Papers

An error efficient and low complexity approximate multi-bit adder for image processing applications