The computer systems security arms race between attackers and defenders are largely taken place in the domain of software systems, but as hardware complexity and design processes have envolved, novel and potent hardware-based security threats are now possible. This article presents Unused Circuit Identification (UCI), an approach for detecting suspicious circuits during design time, and BlueChip, a hybrid hardware/software approach to detaching suspicious circuits and making up for UCI classifier errors during runtime.

Overcoming an untrusted computing base: detecting and removing malicious hardware automatically

Design and fabrication outsourcing has made integrated circuits (IC) vulnerable to malicious modifications by third parties known as hardware Trojans (HT). Over the last decade, the use of side-channel measurements for detecting the malicious manipulation of the ICs has been extensively studied. However, the suggested approaches often suffer from three major limitations: 1) reliance on a trusted identical chip (i.e. golden chip), 2) untraceable footprints of subtle hardware Trojans which remain inactive during the testing phase, and 3) the need to identify the best discriminative features that can be used for separating side-channel signals coming from HT-free and HT-infected circuits. To overcome these shortcomings, we propose a novel neural network design (i.e. HTNet) and a feature extractor training methodology that can be used for HT detection in run time. We create a library of known hardware Trojans and collect electromagnetic and power side-channel signals for each case and train HTnet to learn the best discriminative features based on this library. Then, in the test time we fine tune HTnet to learn the behavior of the particular chip under test. We use HTnet followed by an anomaly detection mechanism in run-time to monitor the chip behavior and report malicious activities in the side-channel signals. We evaluate our methodology using TrustHub [15] benchmarks and show that HTnet can extract a robust set of features that can be used for HT-detection purpose.

HTnet: Transfer Learning for Golden Chip-Free Hardware Trojan Detection

Internet of Things (IoT) applications have been used in a wide variety of domains ranging from smart home, healthcare, smart energy, and Industrial 4.0. While IoT brings a number of benefits including convenience and efficiency, it also introduces a number of emerging threats. The number of IoT devices that may be connected, along with the ad hoc nature of such systems, often exacerbates the situation. Security and privacy have emerged as significant challenges for managing IoT. Recent work has demonstrated that deep learning algorithms are very efficient for conducting security analysis of IoT systems and have many advantages compared with the other methods. This paper aims to provide a thorough survey related to deep learning applications in IoT for security and privacy concerns. Our primary focus is on deep learning enhanced IoT security. First, from the view of system architecture and the methodologies used, we investigate applications of deep learning in IoT security. Second, from the security perspective of IoT systems, we analyse the suitability of deep learning to improve security. Finally, we evaluate the performance of deep learning in IoT system security.

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Deep learning-based security behaviour analysis in IoT environments: A survey

As the internationalization of Integrated Circuit (IC) production increased, the inclusion of deliberately stealthy modification called hardware Trojans has also escalated. A hardware Trojan detection method that works at the gate-level using the netlist of the circuit under test is presented in this paper. The unsupervised machine learning algorithm, K-Means classification is used for categorization. Every net of the circuit is analyzed to determine if the net is genuine or is Trojan infected by the extraction of seven relevant features from every net. The technique has been validated on ISCAS’85 benchmark circuits and parameters like true positive (TP), false negative (FN) and recall (TPR) have been illustrated.

Hardware Trojan Detection Using Machine Learning Technique

Due to the outsourcing of integrated circuit manufacturing to third party vendors. The chances of malicious hardware insertion also got increased. Untrusted foundries can always add Hardware Trojan circuits, which can alter the behavior or working of the integrated circuits. Since new hardware threats are emerging day by day, a generalized solution for threat detection should be defined. Machine learning based threat detection which is widely popular nowadays, it requires handcrafted features. On the contrary, the Deep Learning (DL) class of ML can choose the relevant features and learn, which has been proposed in this paper. Raw circuit features are extracted and fed to the DL model (Deep Stacked Auto Encoder), which could extract features that can aid in Trojan detection. 95% average TPR and 75% average TNR is obtained and which is higher than previously discussed works.

Hardware Trojan Detection Using Deep Learning-Deep Stacked Auto Encoder

A method to detect hardware Trojan in gate-level netlist is proposed using deep learning technique. The paper shows that it is easy to identify genuine nodes and Trojan-infected nodes based on controllability and transition probability values of a given Trojan-infected circuit. The controllability and transition probability characteristics of Trojan-infected nodes show large inter-cluster distance from the genuine nodes so that it is easy to cluster the nodes as Trojan-infected nodes and genuine nodes. From a given circuit, controllability and transition probability values are extracted as Trojan features using deep learning algorithm and clustering the data using k-means clustering. The technique is validated on ISCAS’85 benchmark circuits, and it does not require any golden model as reference. The proposed method can detect all Trojan-infected nodes in less than 6 s with zero false positive and zero false negative detection accuracy.

Hardware Trojan Detection Using Deep Learning Technique

A Deep learning based malicious module identification using Stacked Sparse Autoencoder Network for VLSI circuit reliability

Globalisation of the Integrated Circuit (IC) is making it easy for the adversaries to pirate IC and insert hardware Trojans. Hardware Trojans are detected at an early stage i.e. the RTL design stage by the verification technique by applying all the input patterns exhaustively. But the Trojans are becoming stealthier and they can easily evade the verification technique. In this paper, a transition probability and timing analysis based Trojan detection is proposed. As at each stage the nets are getting filtered out and thus reducing the execution time and complexity of the technique. So the Trojans which evades the design stage detection technique can be easily caught by the proposed technique as it based on the side channel analysis. This method is verified on ISCAS’85 and ISCAS’89 circuits.

Hardware Trojan detection with node reduction using static timing analysis

True random number generation (TRNG) is one of the prominent research areas in present scenario of cryptography and security. It has been reported in the recent past that even TRNG encounters security threats. In order to ensure the security of the random numbers, entropy of random numbers being generated should be high. There are different approaches to generate the random numbers from the physical processes, ranging from jitter to chaos. Various schemes employing the jitter as entropy source have been reported. The usage of jitter in ring oscillator aids in obtaining a high speed real-time random number generation (RNG). On the other hand, the asynchronous architecture ensures high security, which has been implemented in the work. Re-configuring these two architectures develops a RNG with high-speed and security. The statistical tests along with internal tests are conducted to ensure security in the architecture. National Institute of Standards and Technology (NIST) tests validated the unpredictability and randomness of the true random number (TRN) generated.

Realization of Re-configurable True Random Number Generator on FPGA

The exponential growth in technological development boosted the IC industry in production of IC chips in a span of 12–18 months. It has paved way for increased outsourcing which leads to malicious modification by inserting hardware trojans. It becomes necessary to detect these defects before IC fabrication in pre-silicon production stage to save the production cost. In this paper, we propose a method for HT detection using gate level netlist. Extracted features from the netlist of circuits are used for dataset creation. From the extracted features, designed deep learning neural network model figures out salient trojan features required for HT classification of nets into trojan-free and trojan infected nets. In addition to this, data imbalance problem occurs in dataset is taken care by preprocessing data using generative adversarial network. Deep learning-based hardware trojan classifier is evaluated with performance metrics like confusion matrix, F-measure, accuracy for ISCAS’85,’89 benchmark circuits and Trust-Hub circuits. 

M. Priyatharishini

Papers

Hardware Trojan Detection Using Deep Learning Technique

A Deep learning based malicious module identification using Stacked Sparse Autoencoder Network for VLSI circuit reliability

Hardware Trojan detection with node reduction using static timing analysis

Realization of Re-configurable True Random Number Generator on FPGA

Hardware Trojan Detection Using Deep Learning-Generative Adversarial Network and Stacked Auto Encoder Neural Networks