This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node The 15nm OCL is based on a generic predictive state-of-the-art technology node The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes Some of these challenges include double-patterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithography-friendly patterns This paper discusses the development of the library considering the challenges associated with advanced technology nodes

Open Cell Library in 15nm FreePDK Technology

Since Moore’s law driven scaling of planar MOSFETs
faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing
to the presence of multiple (two/three) gates, FinFETs/Trigate
FETs are able to tackle short-channel effects (SCEs) better than
conventional planar MOSFETs at deeply scaled technology nodes
and thus enable continued transistor scaling. In this paper, we
review research on FinFETs from the bottommost device level
to the topmost architecture level. We survey different types of
FinFETs, various possible FinFET asymmetries and their impact,
and novel logic-level and architecture-level tradeoffs offered by
FinFETs. We also review analysis and optimization tools that
are available for characterizing FinFET devices, circuits, and
architectures.

/pdf/finfets-from-devices-to-architectures-3wvjf3zgcz.pdf

FinFETs: From Devices to Architectures

Approximate computing is a new paradigm for designing energy-efficient integrated circuits at the nanoscale. In this paper, we propose efficient imprecise 4:2 and 5:2 compressors by modifying the truth table of the exact compressors to achieve simpler logic functions with fewer output errors. The proposed approach leads to imprecise compressors with significantly fewer transistors and higher performance in comparison with their previous counterparts. Moreover, efficient approximate multipliers are designed based on the proposed imprecise compressors. The circuits are designed using FinFET as one of the leading industrial technologies and are simulated with HSPICE at 7 nm technology node. Furthermore, the approximate multipliers are used in the image processing applications, including image multiplication, sharpening and smoothing, and the peak signal to noise ratio (PSNR) and mean structure similarity index metric (MSSIM) as two important quality metrics are calculated using MATLAB. The results indicate significant improvements regarding performance, energy-efficiency, and the number of transistors compared to the other existing exact and approximate designs. The proposed 4:2 and 5:2 compressors improve the power delay product (PDP), on average by 59% and 68%, and area by 60% and 75%, respectively, in comparison with the previous designs. In addition, the proposed multipliers provide a significant compromise between hardware efficiency and accuracy for approximate computing. The proposed approximate multiplier using both imprecise 4:2 and 5:2 compressors improves the figure of merit, considering both image quality (based on PSNR and MSSIM) and energy efficiency, by 2.35 times as compared to its previous counterparts.

Energy and area efficient imprecise compressors for approximate multiplication at nanoscale

With the emergence of nonplanar CMOS devices at the 22-nm node and beyond, it is highly likely that multigate device adoption will occur in a high-performance process technology, owing to the increased performance and area benefits. In this paper, for the first time, we evaluate symmetric (Symm-ΦG) and asymmetric (Asymm-ΦG) gate-workfunction FinFETs head to head in a high-performance process, using technology computer-aided design 3-D device simulations. We demonstrate that Asymm-ΦG shorted-gate (a-SG) n/p-FinFETs, which use both workfunctions corresponding to typical high-performance metal-gate n/p-FinFETs, are promising, as they can yield over two orders of magnitude lower leakage without excessive degradation in ON-state current, in comparison to Symm- ΦG shorted-gate (SG) FinFETs, placing them in a better position than back-gate biased independent-gate (IG) FinFETs for leakage reduction. Thereafter, we explore the design space of FinFET logic gates, latches, and flip-flops, for optimal tradeoffs in leakage versus delay and temperature, using mixed-mode 2-D device simulations. Elementary logic gates (such as INV, NAND2, NOR2, XOR2, and XNOR2) using Asymm-ΦG SG-mode FinFETs appear to be located optimally in the leakage-delay spectrum, in comparison to the most versatile configurations possible by mixing corresponding Symm-ΦG SG- and IG-mode FinFETs. Latches and flip-flops, however, require an astute combination of Symm-ΦG and Asymm-ΦG FinFETs to optimize leakage, delay, and setup time simultaneously.

Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology

This paper presents a single-ended low-power 7T SRAM cell in FinFET technology. This cell enhances read performance by isolating the storage node from the read path. Moreover, disconnecting the feedback path of the cross-coupled inverters during the write operation enhances WSNM by nearly 7.7X in comparison with the conventional 8T SRAM cell. By using only one bit-line, this cell reduces power consumption and PDP compared to the conventional 8T SRAM cell by 82% and 35%, respectively.

A low-power single-ended SRAM in FinFET technology

This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thick ness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2 GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.

M Rostami

Papers

Dual- $V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits