Dual- $V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

TLDR: This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thick ness optimization required to realize dual-Vth independent-gate FinFETs, enabling a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates.

Abstract: This paper describes the electrode work-function, oxide thickness, gate-source/drain underlap, and silicon thick ness optimization required to realize dual-Vth independent-gate FinFETs. Optimum values for these FinFET design parameters are derived using the physics-based University of Florida SPICE model for double-gate devices, and the optimized FinFETs are simulated and validated using Sentaurus TCAD simulations. Dual-Vth FinFETs with independent gates enable series and parallel merge transformations in logic gates, realizing compact low power alternative gates with competitive performance and reduced input capacitance in comparison to conventional FinFET gates. Furthermore, they also enable the design of a new class of compact logic gates with higher expressive power and flexibility than conventional CMOS gates, e.g., implementing 12 unique Boolean functions using only four transistors. Circuit designs that balance and improve the performance of the novel gates are described. The gates are designed and calibrated using the University of Florida double-gate model into conventional and enhanced technology libraries. Synthesis results for 16 benchmark circuits from the ISCAS and OpenSPARC suites indicate that on average at 2 GHz, the enhanced library reduces total power and the number of fins by 36% and 37%, respectively, over a conventional library designed using shorted-gate FinFETs in 32 nm technology.