Redundant binary (RB) representation is one of the signed-digit number systems originally introduced by Avizienis, which provides carry-propagation-free addition. Since the multiplication of two numbers is generally performed by the addition of partial products, the carry-propagation-free feature of the RB arithmetic can be used to design high-speed multipliers and multiply-and-accumulate units. However, a RB-NB (redundant binary to normal binary) converter is required to provide a 2's-complement representation of the results. Previous research was conducted for the RB-NB converter. In this paper, based on Yen's method and Ling's adder scheme, we propose an improved RB-NB converter. The proposed RB-NB converter shows improvement in area and speed over other methods. The new RB-NB converter has been adopted in our proposed high-performance Complex Arithmetic Signal Processor.

A new redundant binary number to 2's-complement number converter

Complex number arithmetic computations are one of the key arithmetic components in modern digital communication and optical systems. Complex number multiplication and complex number inner-product play a unique role in these applications. In this paper, a complex-number multiplier and complex-number inner-product processor based on a Redundant Binary (RB) representation are presented. This work is an extension of a previous real fixed-point inner-product hardware design. With the proposed algorithms, the complex number multiplication is reduced to parallel RB multiplications, and the complex number inner-product is produced using a RB addition tree. This proposed inner-product processor can be reconfigured or controlled to perform different computations such as inner-product processing or parallel multiplies for real and/or complex numbers. The design results, not only in simplified arithmetic operations, but also in a highly parallel and simple architecture when compared with other methods.

http://ieeexplore.ieee.org/iel5/8452/26621/01187121.pdf

High-speed complex number multiplier and inner-product processor

Truncation in digit-precision is a very important and common operation in embedded system design for bounding the required finite precision and for area-time-power savings. In this paper, we present the use of online arithmetic to provide truncated computations with communication systems as one of the applications. In contrast to truncation in conventional arithmetic, online arithmetic can truncate dynamically and produce both area and time benefits due to the digit-serial nature of computations. This is of great advantage in communication systems where the precision requirements can change dynamically with the environment. While truncation in conventional arithmetic can have significant truncation errors, especially when the output precision is less than the input precision, the redundancy and most significant digit first nature of online arithmetic restricts the truncation error to only the least significant digit of the truncated result. As an application that uses significant truncation in precision, a code matched filter detector for wireless systems is designed using truncated online arithmetic. The detector can provide both hard decisions and soft(er) decisions dynamically as well as interface with other conventional arithmetic circuits or act as a DSP coprocessor. Thus, optimized communication receivers with coexisting conventional arithmetic for saturation and online arithmetic for truncation can now be built. The truncated online arithmetic detector was also verified with a VLSI implementation in an AMI 0.5 mu MOSIS tiny chip process

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Truncated Online Arithmetic with Applications to Communication Systems

A high-performance iterative quadratic convergence fixed-point, real and complex number, divider circuit using a previously developed redundant binary inner-product processor core is presented. The intermediate quotient coefficients are kept in redundant binary (RB) form without converting back to normal binary numbers. A unified multiplier using redundant binary representation for both signed and unsigned numbers is investigated. Goldschmidt and Newton-Raphson division methods are compared and the mathematical equivalence of these two methods is provided.

High-performance divider using redundant binary representation

In this paper, an instruction set architecture is presented for a complex arithmetic signal processor (CASP). CASP is designed to exploit the best features of RISC styled general purpose processors and memory oriented DSP. CASP utilizes the redundant binary (RB) to exploit the single digit carry-propagation property for performance improvement of inner-product unit. Special addressing modes and instructions are designed to provide for faster signal processing. A special register-indirect mode is created for fetching co-processor memory resident dataset elements. The data path on the RB co-processor side is 256-bits wide which allows for processing of large datasets in parallel. Instructions are designed to utilize less than the full width of RB co-processor. The co-processor can perform parallel operations on groups of 8-elements, or two 4-element real TC numbers. The same structure can be alternatively used by instructions for 2-element complex inner-products. An algorithm to detect and correct the bogus or pseudo carry out of RB arithmetic is developed and implemented as a two level hardware process.

https://ieeexplore.ieee.org/iel5/9110/28888/01300163.pdf

Architectural design of a complex arithmetic signal processor (CASP)

A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is presented. The proposed scheme decreases the number of partial products to 50%, compared to other methods, while achieving better speed and area performance and providing pipeline extension opportunities. When modified Booth encoding is used, partial products are reduced by almost 75%, thereby significantly reducing the multiplier addition depth. The design is applicable for digital signal and image processing applications that require inner-product arithmetic, such as digital filters, correlation and convolution. The proposed design is well suited for VLSI implementation, and it can also be embedded as an inner-product core inside a DSP processor or FPGA-based processor.

http://ieeexplore.ieee.org/iel5/7744/21273/00987714.pdf

M. Tull

Papers

The implementation of an efficient and high-speed inner-product processor