The implementation of an efficient and high-speed inner-product processor

TLDR: A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is presented, which decreases the number of partial products to 50%, compared to other methods, while achieving better speed and area performance and providing pipeline extension opportunities.

Abstract: A novel, high-performance fixed-point inner-product processor based on a redundant binary number system is presented. The proposed scheme decreases the number of partial products to 50%, compared to other methods, while achieving better speed and area performance and providing pipeline extension opportunities. When modified Booth encoding is used, partial products are reduced by almost 75%, thereby significantly reducing the multiplier addition depth. The design is applicable for digital signal and image processing applications that require inner-product arithmetic, such as digital filters, correlation and convolution. The proposed design is well suited for VLSI implementation, and it can also be embedded as an inner-product core inside a DSP processor or FPGA-based processor.