A method for the fabrication of microelectronic semiconductor circuits, including the concurrent low pressure deposition of monocrystalline and polycrystalline semiconductor material in a predetermined pattern. In a preferred embodiment, a dielectric isolated circuit is fabricated, by such selective epitaxial growth, and a subsequent oxidation of both the mono- and polycrystalline deposits. By controlling the ratio of the deposition rates, and by controlling the oxidation step, the poly deposit is substantially fully converted to oxide, while the mono is only partly oxidized, leaving a substantially coplanar, isolated matrix of passivated monocrystalline areas in which to fabricate circuit components for interconnection.

Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition

An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

Process for fabricating a bipolar transistor

This invention provides a method for manufacturing a bipolar transistor which comprises steps of selectively forming in the surface of a semiconductor substrate an embedded layer of a conductivity type opposite to that of the substrate, covering the substrate with an insulating layer doped, at the surface thereof with an impurity in the superficial region thereof, removing by etching the insulating layer to form an opening portion through which part of the embedded layer is exposed, simultaneously forming by epitaxial growth a single-crystal semiconductor layer of the same conductivity type as that of the embedded layer on the embedded layer at the opening portion and a polycrystalline semiconductor layer on the insulating layer, diffusing by heating the impurity in the insulating layer into the polycrystalline semiconductor layer to provide a conductivity type opposite to that of the single-crystal semiconductor layer, and successively forming an internal base region and an emitter region in the single-crystal semiconductor layer. The invention also provided a bipolar transistor manufactured by the aforementioned method.

Method of making a bipolar transistor

In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.

Semiconductor device having a miniature junction area and process for fabricating same

A method of forming a semiconductor device having a single crystal silicon substrate, the surface of which includes exposed silicon areas bounded by and coplanar with insulating oxide regions. A polysilicon layer is deposited thereon and annealed to form a single crystal epitaxial region overlying the exposed substrate areas while the regions overlying the oxide areas in the substrate surface may be of polycrystalline form. This structure is applied to NMOS, CMOS, MESFET, and I2 L devices to achieve high packing density, high speed, improved isolation between devices and reduced susceptibility to latch-up.

Localized epitaxy for VLSI devices

A DIELECTRICALLY ISOLATED SSEMICONDUCTOR DEVICE CAN BE MANUFACTURED, THE STRUCTURE IS USEABLE FOR INTERGRATED CIRCUITS, INCLUDING FIELD EFFECT AND/OR BIPOLAR TRANSISTORS, WHEREIN A SIGNIFICANT SAVINGS IN SURFACE AREA AND REDUCTION IN CAPACITANCES CAN BE OBTAINED OVER PRIOR TECHNIQUES. THE METHOD INVOLVES FORMING A LYYER OF DIELECTRIC MATERIAL UPON A SEMI-CONDUCTOR BODY, HAVING A DIFFUSED REGION WHERE A BIPOLAR DEVICE IS TO BE FORMED, AND THE FORMING AN OPENING IN THE LAYER TO EXPOSE A PART OF THE SURFACE OF THE DIFFUSED REGION OF THE SEMICONDUCTOR BODY. AN EQITAXIAL LAYER OF SILICON IS DEPOSITED ON TOP. SINGLE CRYSTAL SILICON WILL GROW OVER THE EXPOSED SILICON AREA AND IF A DIFFUSED REGION IS PRESENT IN THE SUBSTRATE A PEDESTAL WILL OUTDIFFUSE THROUGH THE SAME AREA FROM THE BURIED DIFFUSED REGION. POLYCRYSTALLINE SILICON WILL GROW ON TOP OF THE DIELECTRIC MATERIAL. THE PEDESTAL IS FORMED IN A SINGLE CRYSTAL EPITAXIAL LAYER OF ANOTHER IMPURITY TYPE. TWO OTHER ACTIVE ELEMENTS OF A BIPOLAR TRANSISTOR, SUCH AS THE EMITTER AND INTRINSIC BASE REGIONS, ARE THEN FORMED IN THE SAME SINGLE CRYSTAL EPITAXIAL LAYER WHILE THE INACTIVE AREA, SUCH AS THE EXTRINSIC BASE, IS FORMED IN POLYCRYSTALLINE SILICON, A REACH THROUGH IS MADE THROUGH THE DIELECTRIC LAYER TO THE THIRD ELEMENT OF THE TRANSISTOR, THAT IS COLLECTOR REGION. D R A W I N G

Magdo Ingrid Emese

Papers

Method of forming dielectric isolation for high density pedestal semiconductor devices

Dielektrisch isolierte Halbleiteranordnung und Verfahren zur Herstellung