Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs.

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

The low power design of Very Large Scale Integration (VLSI) system is one of the hot topic in research. In this chapter, the low power design for VLSI based high-speed communication is realized over 28 nm VLSI chip packed in UltraScale Field Programming Gate Array (FPGA) using proposed technique. The high-speed communication system is taken as case study for the low power design of VLSI system. Similarly, various VLSI design system can be realized to achieve the low power VLSI system design goal. High-speed communication systems provide the smooth operation for global internet traffic and requires high power devices and components.IO standard is powerful interface tool that provides low power consumption using the fast signal termination by mean of electrical characteristics. In result for this work, more than 96% power reduction is achieved for VLSI based high-speed communication system, when operated at 500 GHZ, 900 GHz, 10 THz and 17 THz carrier frequencies using the High-Speed Unterminated Logic IO Standard. The power analysis is performed using XPA analyzer in Xilinx suite.

Low Power Design of High Speed Communication System Using IO Standard Technique over 28 nm VLSI Chip

In this paper, we have investigated pipeline and parallel processing architectures of finite impulse response (FIR) filter for efficient field programmable gate array (FPGA) implementation. Our simulation results shows that parallel processing architecture is more efficient as compared to pipeline architecture. Further, it is shown that fast FIR architecture is most suitable as compared to conventional parallel processing architecture due to its hardware complexity reduction. Fast FIR filter architecture shows 25% improvement in area as compared to conventional parallel processing architecture for identical performance.

Investigation of suitable DSP architecture for efficient FPGA implementation of FIR filter

Rice processing, an important feature in rice production involving the transformation of harvested paddy into edible rice, is dependent on the type of rice processing techniques used. The purpose of this paper is to analyze the choice of processing techniques among rice processors in Nigeria.,The study was carried out in Nigeria using structured questionnaires among 410 rice processors selected from four states (Ebonyi, Ekiti, Ogun and Nasarawa) from three geo-political zones (Southeast, Southwest and North-central) of Nigeria. Information on socio-economic characteristics (age, sex, household size, marital status and education) and processing characteristics (experience, paddy source, processing activities, processing techniques, credit and distance) were obtained. Data were analyzed with the use of descriptive statistics and multinomial logistic regression model at 0.05.,The mean age of processors was 47.8±9.9 years, mean household size was 6.5±4.2 persons and 88.7 percent were married. In total, 73.6 percent had formal education and mean years of experience was 16.4±9.2 years. Main processing activities were parboiling and drying (50.0 percent); milling (40.0 percent); and de-stoning (10.0 percent). In all, 65.7, 20.4 and 13.9 percent used traditional and modern techniques (TMTs), traditional techniques (TTs) and purely modern techniques (PMTs), respectively. The probability of choice of TT relative to TMT reduced by years of education (4.5 percent), paddy source (1.8 percent) and distance to processing center (4.4 percent), while probability of choice of PMT relative to TMT increased for male processors (7.3 percent), membership of association(18.0 percent) and other income sources (6.2 percent).,Level of education of processors and reduction in the distance taken to paddy source reduced choice of TTs.,Other income sources increased the choice of PMTs of rice processing in Nigeria.,Processors with high level of education, who also engage in other income generating activities, were able to choose modern processing techniques.,This research was an original research carried out among rice processors in Nigeria.

Choice of processing techniques among rice processors in Nigeria

This paper presents the simulation of reentrant excitation-conduction of cardiac cells realized by coupling 80 active circuits in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo (FHN) model. 1D ring-shaped cable model is designed using Simulink in order to simulate an action potential signal and its conduction for a hardware design by using HDL Coder to automate the model for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) code generation. Then, the VHDL design is functionally verified on a Field Programmable Gate Array (FPGA) Xilinx Virtex-6 board using HDL Verifier proving the model through FPGA-in-the-Loop (FIL) co-simulation approach. It can then be downloaded into a target FPGA device for real-time simulations. This novel approach of prototyping cardiac reentrant excitation-conduction provides a fast and effective FPGA-based hardware implementation flow towards a stand-alone implementation to perform complex real-time simulations compared with manual HDL designs.

FPGA-in-the-loop co-simulation of reentrant arrhythmia mechanism in one dimensional (1D) ring-shaped based on FitzHugh-Nagumo model

Reconfigurable hardware is emerging as the best option for the efficient implementation of complex and computationally expensive signal processing algorithms. Reconfigurable hardware exploits the benefit of high of computational efficiency of hardware as well as flexibility of software implementation. Field Programmable Gate Array (FPGA) which finds wide range of applications in the field of signal processing, wireless communication, image and video processing has gained popularity as a reconfigurable logic over past decade. In this paper, various hardware aspects of reconfigurable such as architectures and models including external coupling and run-time reconfigurable systems have been studied. Moreover, a case study of most widely used commercial FPGA technologies from Xilinx and upcoming three dimensional 3D- FPGA architecture is presented. It is revealed that the reconfigurable hardware can be used in a variety of DSP applications. FPGA implementation of digital signal processing applications show enhanced outcome in terms of speed as compared to software implementation and previously reported architecture.

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An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

In this paper, we present suitable design optimization for area-delay efficient implementation of finite impulse response (FIR) filter on Field Programmable Gate Array (FPGA). Architectural optimization done in MATLAB/Simulink environment, Hardware description language (HDL) netlist produced by System Generator enables emulation on FPGA and also serves as design entry for chip realization. The design of digital filter characterized by minimum critical path and latency, low cost and reduced complexity. Considering above parameters different architectures are implemented such as transpose-form, pipelined filter and parallel processing. Result shows comparison for maximum frequency, resource utilization and reduced latency

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Comparative Analysis and Efficient VLSIImplementation of FIR Filter

/pdf/enhancing-security-of-cloud-based-file-sharing-systems-using-1wxj7mt3.pdf

Mahesh Kadam

Papers

An Overview of Reconfigurable Hardware for Efficient Implementation of DSP Algorithms

Investigation of suitable DSP architecture for efficient FPGA implementation of FIR filter

Comparative Analysis and Efficient VLSIImplementation of FIR Filter

Enhancing Security of Cloud based File Sharing Systems using AES and Proxy-Transformation