An apparatus for interrogating an electronic circuit supported by a substrate includes a tester external to the substrate and comprising an tester transceiver. A testing circuit is supported by the substrate and connected to the electronic circuit. The testing circuit includes a processor and a testing circuit transceiver in communication with the tester transceiver for transmitting instructions from the tester to the processor and for transmitting results of an interrogation from the processor to the tester. The processor being programmed to process instructions from the tester to interrogate the electronic circuit with an interrogation corresponding to the instructions.

Method and apparatus for interrogating electronic equipment components

At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.

Method of Manufacturing a Semiconductor Device

A method and apparatus for interrogating an electronic component (20), includes a body (18 or 102) having an interface (10, 24, 108 or 154) for an interrogating device (48/50 or 106) to use as a conduit in reliably performing multiple discrete interrogations of the electronic component (20) without the interrogating device physically touching the electronic component (20).

Method and apparatus for interrogating an electronic component

A method of testing an electronic device includes measuring radio frequency emissions at a plurality of positions relative to a trusted unit of a particular electronicdevice during operation of the trusted unit, and measuring radio frequency emissions at the same plurality of positions relative to a second unit of the particular electronic device. For each of the plurality of positions, the radio frequency emissions measured from the second unit are compared to the radio frequency emissions measured from the trusted unit. The method then determines whether there is any frequency at which the measured amplitude of the radio frequency emissions from the second unit and the measured amplitude of the radio frequency emissions from the trusted unit exhibit a statistically significant difference.

Detecting malicious hardware by measuring radio frequency emissions

The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Low fabrication cost, high performance, high reliability chip scale package

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Majid Aghababazadeh

Papers

System and apparatus for using test structures inside of a chip during the fabrication of the chip

Technique for evaluating a fabrication of a semiconductor component and wafer

Technique for evaluating a fabrication of a die and wafer

Intra-chip power and test signal generation for use with test structures on wafers

Contactless technique for evaluating a fabrication of a wafer