Patent
Technique for evaluating a fabrication of a semiconductor component and wafer
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TLDR
In this article, the value of a specified performance parameter is determined at a plurality of locations on an active area of a die of the wafer, and evaluation information may then be obtained based on a variance of the values of the performance parameter at the plurality of positions.Abstract:
The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.read more
Citations
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TL;DR: In this article, the value of a specified performance parameter is determined at a plurality of locations on an active area of a die of the wafer, and evaluation information may then be obtained based on a variance of the values of the performance parameter at the plurality of positions.
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Technique for evaluating a fabrication of a die and wafer
TL;DR: In this paper, the value of a specified performance parameter is determined at a plurality of locations on an active area of a die of the wafer, and evaluation information may then be obtained based on a variance of the values of the performance parameter at the plurality of positions.
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References
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Patent
System and method for product yield prediction using device and process neighborhood characterization vehicle
TL;DR: In this article, a system and method for predicting yield of integrated circuits includes a characterization vehicle (12) having at least one feature representative of one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle.
Patent
System and method for product yield prediction
Brian E. Stine,Christopher Hess,John Kibarian,Kimon Michaels,Joseph C. Davis,Purnendu K. Mozumder,Sherry F. Lee,Larg Weiland,Dennis Ciplickas,David M. Stashower +9 more
TL;DR: In this paper, an extraction engine extracts predetermined layout attributes from a proposed product layout and produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process.
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Emission microscopy system
TL;DR: In this paper, an optical emission microscopy system with a macro optic system having a high numerical aperture for obtaining global views of an integrated circuit Device Under Test (DUT) is presented, and images are obtained to form a "global difference" image in which defects, wherever located in the chip, can be discerned by the system operator.
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Testing system for evaluating integrated circuits, a burn-in testing system, and a method for testing an integrated circuit
TL;DR: In this article, a burn-in testing system for evaluating a circuit under test is presented, which includes a burnin board having a plurality of receptacles, at least one of which being sized to receive the test interface circuitry supported by the board and coupled to the receptacles.
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TL;DR: In this paper, a system for functionally testing opto-electronic devices, such as fiber-optic infrared receiver photodiodes, in the integral wafer or other optical port-exposed status is presented.