The vision of ambient intelligence opens a world of unprecedented experiences: the interaction of people with electronic devices is changed as contextual awareness, natural interfaces and ubiquitous availability of information are realized. We analyze the consequences of the ambient intelligence vision for electronic devices by mapping the involved technologies on a power-information graph. Based on the differences in power consumption, three types of devices are introduced: the autonomous or microWatt-node, the personal or milliWatt-node and the static or Watt-node. Ambient intelligent functions are realized by a network of these devices with the computing, communication and interface electronics realized in silicon IC technologies. Three case studies highlight the IC design challenges involved, and show the variety of problems that have to be solved.

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IC Design Challenges for Ambient Intelligence

Means of communicating between modules in a decoding system. A variable-length decoding accelerator communicates with a core decoder processor via a co-processor interface. In one embodiment, other decoding accelerators, in addition to the variable-length decoder, are adapted to provide status data indicative of their status to a co-processor status register. In another embodiment, a decoding accelerator is controlled by providing commands to the accelerator via posted write operations and polling the accelerator to determine whether the command has been performed. In still another embodiment, a first hardware accelerator communicates with a core decoder processor via a co-processor interface and other decoding accelerators, in addition to the first hardware accelerator, are adapted to provide status data indicative of their status to a co-processor status register.

Method of communicating between modules in a decoding system

We propose an access scheme for a synchronous dual- port (DP) SRAM that minimizes the 8T-DP-cell area and maintains cell stability. A priority row decoder circuit and shifted bit- line access scheme eliminates access conflict issues. Using 65 nm CMOS technology (hp90) with the proposed scheme, we fabricated 32 kB DP-SRAM macros. We obtained a 0.71 mum2 8T-DP-cell for which the cell size is only 1.44 times larger than a 6T-single-port (SP)- cell. The bit-density of the fabricated 32 kB DP-RAM macro is 667 kbit/mm2, which is 25% larger than a conventional 8T SRAM. The standby leakage is 27% less because of the small drive-NMOS transistor of the proposed 8T-DP-cell.

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

In an ordered semaphore management system a pending state allows threads not competing for a locked semaphore to bypass one or more threads waiting for the same locked semaphore. The number of pending levels determines the number of consecutive threads vying for the same locked semaphore which can be bypassed. When more than one level is provided the pending levels are prioritized in the queued order.

Flow lookahead in an ordered semaphore management subsystem

There is provided in one embodiment an apparatus having an image sensor array. In one embodiment, the image sensor array can include monochrome pixels and color sensitive pixels. The monochrome pixels can be pixels without wavelength selective color filter elements. The color sensitive pixels can include wavelength selective color filter elements.

Apparatus having hybrid monochrome and color image sensor array

This paper proposes a memory-based architecture implementing the MPEG2 System protocol LSIs, and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 System protocol for both multiplexing and de-multiplexing MPEG2-encoded streams. It consists of a core CPU, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software co-design techniques. The LSIs provide sufficient performance and flexibility for real-time applications of the MPEG2 System protocol.

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A memory-based architecture for MPEG2 System protocol LSIs

PROBLEM TO BE SOLVED: To construct a real time information processing on an information processing system where loaded memories are considerably few by installing only task management, interruption management and semaphore management as functions for realizing a real time processing. SOLUTION: On-chip real time OS 21 has a task management means 21a, an interruption management means 21b and a semaphore management means 21c. The task management means 21a has a multi-task function being a function which can independently process a plurality of tasks by time multiplex and a preemptive schedule function being a function for preferentially processing the task whose priority is higher than the task whose priority is low in accordance with priority given to a plurality of tasks on CPU 11. The interruption management means 21b has a function receiving an interruption event during the execution of the task of any priority. The semaphore management means 21c has the exclusive control function of information transfer among a plurality of tasks. COPYRIGHT: (C)1999,JPO

On-chip real time os

PROBLEM TO BE SOLVED: To build up parallel coding of a picture through area division onto a parallel computer having a plurality of computer resources. SOLUTION: A plurality of single coding sections 2A that encode division pictures in divided areas with a designated coding parameter and output the coding result and an area stream, and an input output entire control section 1A that divides an input picture into a plurality of areas, combines streams from a plurality of the single coding sections 2A into one and controls a plurality of the single coding sections 2A are assigned to a plurality of computer resources. The input output entire control section 1A outputs an instruction of the division picture input and an instruction of the area stream output to a plurality of the single coding sections 2A to control input output timing of a plurality of division pictures and a plurality of the area streams 8, the picture division area information, coding parameter information of each single coding section, coding result information of each single coding section are transmitted/received between the input output entire control section 1A and a plurality of the single coding sections 2A and the information is updated synchronously in the unit of coding processing.

Method for coding parallel software picture and recording medium recording parallel software picture coding program

PROBLEM TO BE SOLVED: To provide an image transmitter, a method thereof, a program and a recording medium which transmits broadband images, using a low-cost unit, and allows a receive side to reproduce the images without time deviation. SOLUTION: The image transmitter comprises: an image dividing means 2 for spatially dividing an input image into a plurality of image regions; a plurality of partial image transmitting means 4 for respectively transmitting a plurality of divided partial images; a plurality of partial image receiving means 6 for respectively receiving the plurality of partial images transmitted over a plurality of transmitting lines 5; and an image reproducing means 8 for synthesizing the plurality of received partial images to reproduce the input image. The transmit side of each transmission lines 5 comprises a pixel group replacing means 3 for replacing a specified pixel group contained on specified scanning lines of the input image with pixel information redundantly expressing the frame numbers of the input image, and an image information compressing means 11 for compressing the information of the partial images the plurality of partial image transmitting means 4 transmit. COPYRIGHT: (C)2004,JPO

Image transmitter, method, program and recording medium

This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability, The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.

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Makoto Endo

Papers

A memory-based architecture for MPEG2 System protocol LSIs

On-chip real time os

Method for coding parallel software picture and recording medium recording parallel software picture coding program

Image transmitter, method, program and recording medium

High-speed software-based platform for embedded software of a single-chip MPEG-2 video encoder LSI with HDTV scalability