We survey recent developments in the design of large-capacity content-addressable memory (CAM). A CAM is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.

https://www.pagiamtzis.com/pubs/pagiamtzis-jssc2006.pdf

Content-addressable memory (CAM) circuits and architectures: a tutorial and survey

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Three dimensional structure memory

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Vertical system integration

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

/pdf/ultralow-power-design-in-near-threshold-region-37ua2hp61u.pdf

Ultralow-Power Design in Near-Threshold Region

An apparatus and method for real-time volume processing and universal three-dimensional rendering. The apparatus includes a plurality of three-dimensional (3D) memory units (24); at least one pixel bus for providing global horizontal communication (34); a plurality of rendering pipelines; at least one geometry bus (46); and a control unit (38). The apparatus includes a block processor having a circular ray integration pipeline for processing voxel data and ray data. Rays are generally processed in image order thus permitting great flexibility (e.g., perspective projection, global illumination). The block processor includes a splatting unit and a scattering unit. A method for casting shadows and performing global illumination in relation to light sources, which includes sweeping a two dimensional array of rays through the volume, can also be implemented with the apparatus. A method for approximating a perspective projection includes using parallel projection.

Apparatus and method for volume processing and rendering

A multiprocessor system has a plurality of processors and a network system linking said processors to thereby process a given load written by a logic programming language According to an initial load balancing algorithm, each processor independently and dynamically selects an initial load segment thereof from the given load by use of a system information representative of characters of the multiprocessor system without transferring information between the processors, whereby an initial load balancing is obtained in the multiprocessor system According to a load balancing algorithm for reproducing working environments which is performed after performing the initial load balancing algorithm, a partial load segment of a first processor is shared to a second processor In this case, the first processor generates a history information representative of the working environment thereof, but the amount of the history information is smaller than that of the whole working environment of the first processor This history information is supplied to the second processor wherein the working environment of the first processor is reproduced by use of the history information Thereafter, the second processor processes the partial load segment of the first processor by use of the reproduced working environment of the first processor while the first processor processes the load segment thereof Thus, the present multiprocessor system can reduce the amount of the transferring information remarkably less than that of the conventional multiprocessor system, whereby the load balancing can be performed with a high speed

Multiprocessor system and a method of load balancing thereof

A parallel algorithm, in order to extract parametric curves from a two-dimensional (2-D) image space, is proposed. It is based on the Hough transform (HT) and uses the content addressable memory (CAM) as the main processor. A set of simulated results for circular shape extraction are presented in order to demonstrate its merit. Hence, voting, thresholding, and three-dimensional (3-D) peak extraction are efficiently performed within the CAM. In addition, and in order to reduce the quantization errors, a weighted AT algorithm (WHT), which uses a weighted voting is proposed. Experimental results indicate that a real-time shape extraction for an image 256/spl times/256 can be achieved within a small amount of hardware. Therefore, CAM-based HT can be considered as a promising attraction for next generation pattern recognition platforms.

On using the CAM concept for parametric curve extraction

An image processing apparatus for extracting lines from an image using the Hough transform. A processor element is assigned to each quantization point in a Hough space. Each processor element calculates, for each scanning line of the image, intersections of the scanning line and the line corresponding to this processor element once per scanning line. A black pixel (a Hough transform object point) on the scanning line is also obtained sequentially. The coordinate values of the intersection are compared with those of the Hough transform object point, and when they agree, voting to a ballot box memory of the processor element is performed. The voting results become Hough transform data. This makes it possible to implement a high speed Hough transform, and to reduce the size of the apparatus.

Image processing method and apparatus for extracting lines from an image by using the Hough transform

For real-time image-processing applications, a highly parallel system that exploits parallelism is desirable. A content addressable memory (CAM), or an associative processor, that can perform various types of parallel processing with words as the basic unit is a promising component for creating such a system because of its suitability for LSI implementation. Conventional CAM LSI's, however, have neither efficient function nor enough capacity for pixel-parallel processing. This paper describes a fully parallel 1-Mb CAM LSI. It has advanced functions for processing various pixel-parallel algorithms, such as mathematical morphology and discrete-time cellular neural networks. Moreover, since it has 16-K words, or processing elements (PEs), which can process 128/spl times/128 pixels in parallel, a board-sized pixel-parallel image-processing system can be implemented using several chips. A chip capable of operating at 56 MHz and 2.5 V was fabricated using 0.25-/spl mu/m full-custom CMOS technology with five aluminum layers. A total of 15.5 million transistors have been integrated into a 16.1/spl times/17.0 mm chip. Typical power dissipation is 0.25 W. Processing performance of various update and data transfer operations is 3-640 GOPS. This CAM LSI will make a significant contribution to the development of compact, high-performance image-processing systems.

Takeshi Ogura

Papers

Multiprocessor system and a method of load balancing thereof

On using the CAM concept for parametric curve extraction

Image processing method and apparatus for extracting lines from an image by using the Hough transform

A fully-parallel 1 Mb CAM LSI for real-time pixel-parallel image processing

A parallel algorithm for real-time object recognition