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M

Manish N. Shah

Researcher at Freescale Semiconductor

Publications -  12
Citations -  473

Manish N. Shah is an academic researcher from Freescale Semiconductor. The author has contributed to research in topics: Baseband & Transceiver. The author has an hindex of 9, co-authored 11 publications receiving 469 citations.

Papers
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Journal ArticleDOI

A Single–Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and ${+}$ 90 dBm IIP2

TL;DR: This paper describes the design and performance of a 90 nm CMOS SAW-less receiver with DigRF interface that supports 10 WCDMA bands and 4 GSM bands and results in current drain and die area savings as well as improved noise.
Journal ArticleDOI

A single-chip tri-band (2100, 1900, 850/800 MHz) WCDMA/HSDPA cellular transceiver

TL;DR: The RF transceiver is integrated with the baseband signal processing and associated passives in a 165-pad package, resulting in the first tri-band 3G radio transceiver with a digital interface which requires no external components.
Patent

High performance CMOS radio frequency receiver

TL;DR: In this paper, a high performance radio frequency receiver includes a low-noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between inphase and Quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal
Patent

Split channel receiver with very low second order intermodulation

TL;DR: In this paper, a high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents.
Patent

Mixer circuits for second order intercept point calibration

TL;DR: In this paper, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixers.