Thermal control of power electronics cabinets requires thermal characterization under multiple length scales and transport modes. Detailed numerical calculations or measurements are often time consuming or simply unfeasible. An efficient multiscale thermal modeling methodology is proposed for electronic cabinets with hybrid liquid, forced air convection, and thermoelectric cooling. Compact models are developed for complex components such as air-cooled heat sinks, thermoelectric coolers, microchannel coolers, and liquid-to-air heat exchangers. These models are validated through detailed simulations or experimental measurements and utilized in system level simulation subsequently. Reduced order modeling based Proper orthogonal decomposition is used to model the full system. A combination of compact modeling at the component level and reduced order modeling at system level is achieved. Performance and limitations of this approach are addressed.

Reduced order modeling of power electronics cabinet with double-sided cooling

The trends in the electronics packaging industry towards miniaturization have resulted in increased I/O over a smaller printed circuit board area. Simultaneously the power output of chips has steadily increased resulting in ever increasing watt densities. These two trends of smaller packaging and higher power have driven the packaging industry towards area array packages such as Ball Grid Array (BGA), Chip Scale Packages (CSP) and flip chips. Though flip chips are not commonly used in a Chip-on-Board format (issues with rework of underfill), it is becoming the technology of choice for 1/sup st/ level packaging. The reason for this is that flip chip designs provide higher I/O density, better electrical performance, reduced cost and improved thermal performance. The trend towards increasing chip power densities makes this last advantage of particular interest to board designers and thermal engineers. The focus of this paper is to compare the thermal performance of wire bonded and flip chip CSP's. Compact models have been developed for both configurations and will be discussed in detail. This paper will also compare the commonly used two-resistor compact model to detailed chip model.

Comparison of the thermal performance of wire bonded and flip chip CSP's

The need for compact models for ICs is a well-recognized problem in electronics cooling simulations of systems containing multiple PCBs and many devices per board. The disparate length scales inherent in the problem and the necessity of resolving these size scales renders the computational problem intractable. Many resistance-capacitance (RC) network compact models have been proposed in the literature. We present a methodology to automatically construct both the topology and characteristics of the reduced-order or compact models of devices (primarily Integrated Circuit (IC) packages) for use in system-level simulations using the multigrid operator. The multigrid technique has been extensively used over the past 20 years to accelerate the solution of liner systems. In addition to automatically generating both the RC network topology and its values, the procedure is general enough to be applicable for complex IC device types like Multi-Chip Modules (MCMs), stack up dies, distributed sources on the die, DC-DC converters and devices such as hard disk drives.Copyright © 2003 by ASME

Manoj Nagulapally

Papers

Development of Compact Models for Electronics Cooling: Using the Multigrid Operator to Generate Reduced Order Description of Devices

Development of Compact Models for Electronics Cooling: Using the Multigrid Operator to Generate Reduced-Order Description of Devices