Memristive devices are electrical resistance switches that can retain a state of internal resistance based on the history of applied voltage and current. These devices can store and process information, and offer several key performance characteristics that exceed conventional integrated circuit technology. An important class of memristive devices are two-terminal resistance switches based on ionic motion, which are built from a simple conductor/insulator/conductor thin-film stack. These devices were originally conceived in the late 1960s and recent progress has led to fast, low-energy, high-endurance devices that can be scaled down to less than 10 nm and stacked in three dimensions. However, the underlying device mechanisms remain unclear, which is a significant barrier to their widespread application. Here, we review recent progress in the development and understanding of memristive devices. We also examine the performance requirements for computing with memristive devices and detail how the outstanding challenges could be met.

Memristive devices for computing

In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

Metal–Oxide RRAM

Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitride-oxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

Overview of candidate device technologies for storage-class memory

A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.

Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM

Storage-class memory (SCM) combines the benefits of a solidstate memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage. Such a device would require a solid-state nonvolatile memory technology that could be manufactured at an extremely high effective areal density using some combination of sublithographic patterning techniques, multiple bits per cell, and multiple layers of devices. We review the candidate solid-state nonvolatile memory technologies that potentially could be used to construct such an SCM. We discuss evolutionary extensions of conventional flash memory, such as SONOS (silicon-oxide-nitrideoxide-silicon) and nanotraps, as well as a number of revolutionary new memory technologies. We review the capabilities of ferroelectric, magnetic, phase-change, and resistive random-access memories, including perovskites and solid electrolytes, and finally organic and polymeric memory. The potential for practical scaling to ultrahigh effective areal density for each of these candidate technologies is then compared.

https://researcher.watson.ibm.com/researcher/files/us-gwburr/NVMcandidates_IBMJRD.pdf

Overview of candidate device technologies for storage-class

A non-volatile resistive switching mechanism based on trap-related space-charge-limited-conduction (SCLC) is proposed Excellent memory characteristics have been demonstrated using near-stoichiometric cuprous oxide (CuxO) metal-insulator-metal (MIM) structures: low-power operation, fast switching speed, superior temperature characteristics, and long retention This MIM memory cell is fully compatible with standard CMOS process The proposed switching mechanism is a strong contender for high density and low cost memory applications

Non-volatile resistive switching for advanced memory applications

In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.

Diode and resistive memory device structures

The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

Metal-insulator-metal-insulator-metal (MIMIM) memory device

In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Test structures for development of metal-insulator-metal (MIM) devices

An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H2. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H2. A glue layer may be provided between the first layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.

Manuj Rathor

Papers

Non-volatile resistive switching for advanced memory applications

Diode and resistive memory device structures

Metal-insulator-metal-insulator-metal (MIMIM) memory device

Test structures for development of metal-insulator-metal (MIM) devices

Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device