The technological development is enabling the production of increasingly complex electronic systems. All such systems must be verified and tested to guarantee their correct behavior. As the complexity grows, testing has become one of the most significant factors that contribute to the total development cost. In recent years, we have also witnessed the inadequacy of the established testing methods, most of which are based on low-level representations of the hardware circuits. Therefore, more work has to be done at abstraction levels higher than the classical gate and register-transfer levels. At the same time, the automatic test equipment based solutions have failed to deliver the required test quality. As a result, alternative testing methods have been studied, which has led to the development of built-in self-test (BIST) techniques. In this thesis, we present a novel hybrid BIST technique that addresses several areas where classical BIST methods have shortcomings. The technique makes use of both pseudorandom and deterministic testing methods, and is devised in particular for testing modern systems-on-chip. One of the main contributions of this thesis is a set of optimization methods to reduce the hybrid test cost while not sacrificing test quality. We have devel oped several optimization algorithms for different hybrid BIST architectures and design constraints. In addition, we have developed hybrid BIST scheduling methods for an abort-on-first-fail strategy, and proposed a method for energy reduction for hybrid BIST. Devising an efficient BIST approach requires different design modifications, such as insertion of scan paths as well as test pattern generators and signature analyzers. These modifications require careful testability analysis of the original design. In the latter part of this thesis, we propose a novel hierarchical test generation algorithm that can be used not only for manufacturing tests but also for testability analysis. We have also investigated the possibilities of generating test vectors at the early stages of the design cycle, starting directly from the behavioral description and with limited knowledge about the final implementation. Experiments, based on benchmark examples and industrial designs, have been carried out to demonstrate the usefulness and efficiency of the proposed methodologies and techniques.

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Hybrid Built-In Self-Test and Test Generation Techniques for Digital Systems

Part 1: Application Mapping and Communication Infrastructure: Virtualization in NOCs--Enhanced MPSOC Robustness and Performance Verification.-HW Support to Exploit Parallelism in Homogeneous and Heterogeneous Multicore System-on-Chip.-PALLAS: Mapping Applications onto Manycore.-Part 2: Reconfigurable Hardware in Multiprocessor Systems: Adaptive Multiprocessor System on Chip Architecture.-Designing FPGA Systems with Many Processors.-Part 3: Physical Design of Multiprocessor Systems: Design tools and methods for chip physical design.-Challenges in Physical Design for Multi- and Manycore Hardware Architectures.

Multiprocessor System-on-Chip

In this paper, circuit failure prediction by timing degradation is used to monitor semiconductor aging, which is a safety-critical problem in the automotive market. Reliability and variability issues are worsening with device scaling down. For safe operation, we propose on-chip, on-line aging monitoring. A novel aging sensor (to be selectively inserted in key locations in the design and to be activated from time to time) is proposed. The aging sensor is a programmable delay sensor, allowing decision-making for several degrees of severity in the aging process. It detects abnormal delays, regardless of their origin. Hence, it can uncover “normal” aging (namely, due to NBTI) and delay faults due to physical defects activated by long circuit operation. The proposed aging sensor has been optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Moreover, the area overhead of the new architecture is significantly less than the one of other aging sensors presented in the literature. Simulation results with a 65 nm sensor design are presented, ascertaining its usefulness and its low sensitivity, in particular to process variations.

Low-sensitivity to process variations aging sensor for automotive safety-critical applications

This paper presents a new approach on aging sensors for synchronous digital circuits. An adaptive error-prediction flip-flop architecture with built-in aging sensor is proposed, performing on-line monitoring of long-term performance degradation of CMOS digital systems. The main advantage is that the sensor's performance degradation works in favor of the predictive error detection. The sensor is out of the signal path. Performance error prediction is implemented by the detection of late transitions at flip-flop data input, caused by aging (namely, due to NBTI), or to physical defects activated by long lifetime operation. Such errors must not occur in safety-critical systems (automotive, health, space). A sensor insertion algorithm is also proposed, to selectively insert them in key locations in the design. Sensors can be always active or at pre-defined states. Simulation results are presented for a balanced pipeline multiplier in 65 nm CMOS technology, using Berkeley Predictive Technology Models (PTM). It is shown that the impact of aging degradation and/or PVT (Process, power supply Voltage and Temperature) variations on the sensor enhance error prediction.

Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on user's requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Predictive error detection by on-line aging monitoring

Electronic systems for safety-critical automotive applications must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is long-term performance degradation due to aging. For safe operation, aging monitoring should be performed on chip, namely using built-in aging sensors (activated from time to time). The purpose of this paper is to present a novel programmable nanometer aging sensor. The proposed aging sensor allows several levels of circuit failure prediction and exhibits low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Simulation results with a 65 nm sensor design are presented, that ascertain the usefulness of the proposed solution.

Programmable aging sensor for automotive safety-critical applications

In nanoscale FPGAs, variability and aging significantly limit performance. In this paper, a novel aging monitoring methodology for FPGA-based designs to mitigate those effects is proposed. Local sensors are embedded in the configured functionality, monitoring critical paths, at production or during product lifetime. No design freeze (slice and routing locked) is required. When sensors observe a user's defined time guardband violation, safe operation is endangered and action can be triggered, either to reduce clock frequency or to increase core VDD. Simulation and experimental results are presented, using Spartan 6 boards and vendor tools. The testbench uses a Data Acquisition (DAQ) system with Triple Modular Redundancy (TMR) architecture and a Built-In Self-Test (BIST) infrastructure. It is shown that local sensors will anticipate system failure. Various devices are also used to analyze sensitivity to process variations.

Aging monitoring with local sensors in FPGA-based designs

Functional test has long been viewed as unfitted for high-quality production test. The purpose of this paper is to propose a RTL-based test generation methodology which can rewardingly be used both for design validation and to enhance the test effectiveness of classic, gate-level test generation. The proposed methodology leads to high Defects Coverage (DC) and to relatively short test sequences, thus allowing low-energy operation in test mode. The test effectiveness, regarding DC, is shown to be weakly dependent on the structural implementation of the behavioral description. The usefulness of the methodology is ascertained using the VeriDOS simulation environment and the CMUDSP and Torch ITC'99 benchmark circuits.

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems

The implementation of complex functionality in low-power (LP) nano-CMOS technologies must be carried out in the presence of enhanced susceptibility to PVT (Process, power supply Voltage and Temperature) variations. VT variations are environmental or operation-dependent parametric disturbances. Power constraints (in normal and test mode) are critical, especially for high-performance digital systems. Both dynamic and leakage power induce variable (in time and space) thermal maps across the chip. PVT variations lead to timing variations. These should be accommodated without losing performance. Dynamic, on-line time management becomes necessary. The purpose of this paper is to present a VT-aware time management methodology which leads to improved PVT tolerance, without compromising performance or testability. First, the methodology is presented, highlighting its characteristics and limitations. Its underlying principle is to introduce additional tolerance to VT variations, by time borrowing, dynamically controlling the time of the clock edge trigger driving specific memory cells (referred to as critical memory cells, CME). VT variations are locally sensed, and dynamic delay insertion in the clock signal driving CME is performed, using Dynamic Delay Buffer (DDB) cells. Then, methodology automation, using the proprietary DyDA tool, is explained. The methodology is proved to be efficient, even in the presence of process variations. Finally, it is shown that VT tolerance insertion does not necessarily reduce delay fault detection, as multi-V DD or multi-frequency self-test can be used to recover detection capability.

Marcelino B. Santos

Papers

Programmable aging sensor for automotive safety-critical applications

Aging monitoring with local sensors in FPGA-based designs

RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems

Time Management for Low-Power Design of Digital Systems

Ultra low power capless LDO with dynamic biasing of derivative feedback