Showing papers in "Microelectronics Journal in 2013"

TL;DR: The read operation of memristor-based memories is investigated and a new technique for solving the sneak paths problem by gating the memory cell using a three-terminal memistor device is introduced.

TL;DR: A new 8T SRAM cell, which employs a single bitline scheme to perform the write and read operations, is proposed, which enhances the write ability and read stability by cutting off the feedback loop of the inverter pair, thereby eliminating the read and write constraints on the transistor dimensions.

TL;DR: A model of Carbon Nanotube Field Effect Transistors (CNTFETs) directly and easily implementable in simulation SPICE software for electronic circuit design and a new procedure, based on a best-fitting between the measured and simulated values of output device characteristics, is proposed.

TL;DR: The noise canceling technique can improve noise figure and the current-reused structure to decrease the total power consumption instead of using a cascade stage is used and the series inductor peaking extends the bandwidth.

TL;DR: The novel design of a low-voltage low-power voltage rectifier based on bulk-driven (BD) winner-take-all (WTA) circuit, specifically designed for battery-powered implantable and wearable medical devices is introduced.

TL;DR: A new secure logic, called charge-sharing symmetric adiabatic logic (CSSAL), is proposed for resistance against differential power analysis (DPA) attacks, and shows its significant power reduction compared to conventional secure logic styles and its efficient resistance to DPA attacks.

TL;DR: A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths.

TL;DR: The results show that the performance of TECs has been improved by reducing the TEC's size and ratio of length to cross-sectional area, resulting in a maximum cooling temperature difference of 88?C, a cooling power density of 1000Wcm-2 and a short response time on the order of milliseconds.

TL;DR: A very good agreement of analytically modeled results with the TCAD simulated results for the three-terminal (3T) and four-Terminal (4T) Si-nTFET device was found.

TL;DR: This review infers that future LNAs suitable for SDR must be highly linear and scalable with future technology nodes.

TL;DR: A novel low voltage self-biased high swing cascode current mirror employing bulk-driven NMOS transistors using CMOS technology is proposed and compared with the conventional SHCCM, showing improvement achieved through the proposed circuit.

TL;DR: A modified three-stage UWB LNA with inter-stage inductors with forward Body-Biased technique used to reduce threshold voltage and power consumption at the first and third stages and a push-pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance.

TL;DR: This paper presents two low power UWB LNAs with common source topology based on an output buffer which is used by a common source amplifier with shunt-shunt feedback, and the power reduction is achieved by the current-reused technique.

TL;DR: A new merging is named bulk-driven quasi-floating gate (BD-QFG)* technique and in order to demonstrate its advantages in compassion to BD and QFG ones, this paper presents a comparison study of three ULV differential difference current conveyor (DDCC) blocks based on BD, QFG and BD-Q FG techniques.

TL;DR: This paper analyzes DML gates operation in the sub- and near-threshold regions by employing a recently proposed transregional model for low supply voltages and Monte Carlo simulations are shown to demonstrate the DML immunity to process variations.

TL;DR: A new low-voltage MOS current mode logic (MCML) topology for an exclusive-OR (XOR) gate using triple-tail cell concept is proposed and the performance is compared with the traditional MCML XOR gate for each design case.

TL;DR: A 2D analytical model for the triple material surrounding gate MOSFET (TMSG) is developed by solving the Poisson equation and it is well validated and compared with the MEDICI simulation results.

TL;DR: A structure based model of an organic thin film transistor (OTFT) and analyzes its device physics and the model is validated in terms of electrical characteristics and performance parameters for both top and bottom contact structures.

TL;DR: Dual-spacer dual-rail delay-insensitive Logic (D^3L), presented in this paper, is able to mitigate both power- and timing-based side-channel attacks.

TL;DR: The IC based design methodology and its application to the next generation BSIM6 compact MOSFET model, which helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions is discussed.

TL;DR: An improved memristor-based relaxation oscillator which offers higher frequency and wider tunning range than the existing reactance-less oscillators and can be fully integrated on-chip providing an area-efficient solution is presented.

TL;DR: The abilities of a Scanning Thermal Microscopy method to characterize the thermal conductivity of insulating materials and thin films used in microelectronics and microsystems are reported on.

TL;DR: A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18µm CMOS technology in this paper.

TL;DR: Three architectures targeting Double Precision (D.P.) multiplier, with one being capable of performing run-time-reconfigurable (RTR) dual Single Precision (S.P) multiplication operation, are presented.

TL;DR: This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation, and shows the resulting chaotic output to pass the NIST SP.

TL;DR: Simulation results of benchmark circuits indicate that the crossbar cells can be combined with CMOS cells to achieve tradeoff between circuit area and speed, and results show that crossbar-based circuits have much smaller area while CMOS circuits show better performance in terms of delay.

TL;DR: It is shown, that the use of midgap Schottky-barrier source and drain contacts are the key enabler for this device concept to be functional and make the presented NWFET-technology suitable for the fabrication multi-purpose devices for many applications.

TL;DR: An electronically tunable universal voltage-mode biquadratic filter with single input and five outputs is introduced, which provides an orthogonal electronic control of its natural angular frequency and quality factor by adjusting only bias currents of the DDCCTAs for the fixed values of capacitors.

TL;DR: An electronically tunable universal voltage-mode biquadratic filter with single input and four outputs using one differential difference current conveyor transconductance amplifier (DDCCTA), two resistors and two grounded capacitors is proposed.

TL;DR: Two main strategies are studied in this paper to form static DCVS-based standard ternary fundamental logic components in digital electronics, which demonstrate their robustness and efficiency even in the presence of PVT variations.