A high-resolution time-to-digital converter (TDC) implemented in a general purpose field-programmable-gate-array (FPGA) is presented. Dedicated carry lines of an FPGA are used as delay cells to perform time interpolation within the system clock period and to realize the fine time measurement. Two Gray-code counters, working on in-phase and out-of-phase system clocks respectively, are designed to get the stable value of the coarse time measurement. The fine time code and the coarse time counter value, along with the channel identifier, are then written into a first-in first-out (FIFO) buffer. Tests have been done to verify the performance of the TDC. The resolution after calibration can reach 50 ps

A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays

The motivation of this paper is to implement a fully fledged FPGA-Based TDC in XILINX XC4VFX60 FPGAs, with the features of Self-Test, temperature variation compensation and trigger-matching. Self-Test is performed with the statistical methods and gives the resolution of delay chain at its temperature and supplied voltage. The resolution changes with the environment temperature, and the corresponding value was recorded by Self-Test from 30∼60 °C for compensation. After compensation and INL calibration, the RMS of time measurement remains less than 30 ps per channel of the total six, and the resolution is about 50 ps. Trigger-matching is implemented using content addressable memory with the two parameters: trigger-latency and matching window programmable.

A fully fledged TDC implemented in field-programmable-gate-arrays

We present the design, operation and test results of a time counter that has an equivalent resolution of 2.9 ps, a measurement uncertainty at the level of 6 ps, and a measurement range of 10 s. The time counter has been implemented in a general-purpose reprogrammable device Spartan-6 (Xilinx). To obtain both high precision and wide measurement range the counting of periods of a reference clock is combined with a two-stage interpolation within a single period of the clock signal. The interpolation involves a four-phase clock in the first interpolation stage (FIS) and an equivalent coding line (ECL) in the second interpolation stage (SIS). The ECL is created as a compound of independent discrete time coding lines (TCL). The number of TCLs used to create the virtual ECL has an effect on its resolution. We tested ECLs made from up to 16 TCLs, but the idea may be extended to a larger number of lines. In the presented time counter the coarse resolution of the counting method equal to 2 ns (period of the 500 MHz reference clock) is firstly improved fourfold in the FIS and next even more than 400 times in the SIS. The proposed solution allows us to overcome the technological limitation in achievable resolution and improve the precision of conversion of integrated interpolators based on tapped delay lines.

https://iopscience.iop.org/article/10.1088/0957-0233/24/3/035904/pdf

A 2.9 ps equivalent resolution interpolating time counter based on multiple independent coding lines

We present the design and test results of a new time-to-digital converter based on the cyclic pulse shrinking method and implemented in a field-programmable gate array (FPGA) device. The pulse shrinking is realized in a loop containing two complementary delay lines. The first line shrinks, and the second line stretches the duration time of a circulating pulse; hence, the length ratio of the lines determines the pulse-shrinking capability of the converter. This resolution control mechanism is different from the bias adjustment typically used in complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) pulse-shrinking elements. Two forms of representation of a measured time interval (the pulse width and the time interval between two pulses) are utilized in the described converter to improve the efficiency of resolution control. To diminish the jitter of the edges of a circulating pulse and, consequently, to increase the precision of the converter, a two-stage conversion is introduced. The first stage, having a low resolution, rapidly shortens the measured pulse, thus limiting the number of cycles, whereas the second stage provides a final high resolution within a narrow time interval range. The optimal resolution of the first conversion stage is theoretically derived. Mostly, the same logical resources of the FPGA device are utilized in both conversion stages; thus, the overall area overhead of the converter is reduced. The converter has a resolution of 42 ps and a measurement uncertainty of below 56 ps within the measurement range of 11.5 ns. The converter has been implemented in a general-purpose reprogrammable device Spartan-3 (Xilinx).

An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

Dynamic development in science and technology in the second half of the twentieth century caused, among others, an increase in the interest in methods and techniques for precise measurement of time interval that elapses between two physical events The main objective of the meters which are used for such purposes is the creation of a numerical representation of the measured time interval with as high accuracy and precision as possible Since the result of measurement is usually presented in digital form, this operation is called a time-to-digital (T/D) conversion, while measuring devices are universally called time-to-digital converters (TDCs) In this chapter, the most representative methods and techniques used for the measurement of time interval with high resolution and precision are described This includes time stretching, time-to-amplitude followed by amplitude-to-digital conversion, the counting method, direct time-to-digital conversions with a digital delay line in the single and Vernier versions, as well as single- and two-stage interpolation methods

Time-to-Digital Converters

High-resolution time-interval measuring system implemented in single FPGA device

Long term instability of frequency and phase fluctuations of the clock signal are significant source of the measurement error in the precise time-interval measurement systems. In this paper the problem of clock signal instability, fluctuations caused by accumulated clock jitter and their influence on the precision of the timeinterval measurement system implemented in the programmable CMOS FPGA devices are discussed. The presented method enables jitter characterization of the reference-clock. Moreover, the time-interval-error in the range up to several miliseconds can be easily and quickly calculated using only two parameters obtained during the calibration process. The described method can be applied in measurement instruments with a precise timebase.

/pdf/accumulated-jitter-measurement-of-standard-clock-oscillators-2ytdb1c4gv.pdf

Accumulated jitter measurement of standard clock oscillators

The ultrasonic flowmeter which is described in this paper, measures the transit of time of an ultrasonic pulse. This device consists of two ultrasonic transducers and a high resolution time interval measurement module. An ultrasonic transducer emits a characteristic wave packet (transmit mode). When the transducer is in receive mode, a characteristic wave packet is formed and it is connected to the time interval measurement module inputs. The time interval measurement module allows registration of transit time differences of a few pulses in the packet. In practice, during a single measuring cycle a few time-stamps are registered. Moreover, the measurement process is also synchronous and, by applying the statistics, the time interval measurement uncertainty improves even in a single measurement. In this article, besides a detailed discussion on the principle of operation of the ultrasonic flowmeter implemented in the FPGA structure, also the test results are presented and discussed.

/pdf/ultrasonic-flow-measurement-with-high-resolution-1bqwzyooad.pdf

Ultrasonic flow measurement with high resolution

Methods of time interval measurement can be divided into asynchronous and synchronous approaches. It is well known that in asynchronous methods of time-interval measurement, uncertainty can be reduced by using statistical averaging. The motivation of this paper is an investigation of averaging in time interval measurements, especially in a synchronous measurement. In this article, authors are considering the method of averaging to reduce the influence of quantization error on measurement uncertainty in synchronous time-interval measurement systems, when dispersion of results, caused by noise is present. A mathematical model of avera ging, which is followed by the results of numerical simulations of averaging of measurement series is presented. The analysis of results leads to the conclusion that in particular conditions the influence of the quantization error on measurement uncertainty can be minimized by statistical averaging, similar to asynchronous measurements.

/pdf/quantization-error-in-time-to-digital-converters-3u80ljflsp.pdf

Quantization error in time-to-digital converters

Measurement of the distribution random error describing a high precision multi-tapped delay lines with coding registers module is important from the perspective of construction high-resolution time-to-digital converters. Knowledge of this distribution allows to optimize the process of implementation Multi-Tapped Delay Lines in programmable structures, thus obtaining the converters with much improved processing performance. In this article a new method for optical measuring of the delay line characteristics is presented. Using this method, the distributions of probabilities of counts in each time-channels are also executed. Finally, the experimental results obtained from optical and widely used a statistical code-density test method were also compared.

Marcin Kowalski

Papers

High-resolution time-interval measuring system implemented in single FPGA device

Accumulated jitter measurement of standard clock oscillators

Ultrasonic flow measurement with high resolution

Quantization error in time-to-digital converters

An optical method for the time-to-digital converters characterization