Nowadays, sorting is an important operation for several real-time embedded applications. It is one of the most commonly studied problems in computer science. It can be considered as an advantage for some applications such as avionic systems and decision support systems because these applications need asorting algorithm for their implementation. However, sorting a big number of elements and/or real-time decision making need high processing speed. Therefore, accelerating sorting algorithms using FPGA can be an attractive solution. In this paper, we propose an efficient hardware implementation for different sorting algorithms (BubbleSort, InsertionSort, SelectionSort, QuickSort, HeapSort, ShellSort, MergeSort and TimSort) from high-level descriptions in the zynq-7000 platform. In addition, we compare the performance of different algorithms in terms of execution time, standard deviationand resource utilization. From the experimental results, we show that the SelectionSort is 1.01-1.23 times faster than other algorithms when N < 64; Otherwise, TimSortis the best algorithm.

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A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis

In this work, we present a soft dual-processor system that, as a distinctive feature, seamlessly integrates a partially run-time reconfigurable 128-bit SIMD engine Importantly, the SIMD engine is tightly coupled to both scalar CPUs and it is shared amongst them with the purpose of drastically improving overall area utilization We show that the proposed SIMD engine increases performance-per-area and that it can be used to substantially accelerate time consuming kernels for a set of media applications

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A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine

Sorting algorithms are one of the most commonly used in computer science. They can be seen as a pillar for some applications such as decision support systems, path planning, etc. However, sorting large number of elements needs high computation rate. Consequently, accelerating sorting algorithms using hardware implementation is an interesting solution to speed up computations. The purpose of this paper is to develop a hardware accelerated version of TimSort and MergeSort algorithms from high level descriptions. The algorithms are implemented using Zynq-7000 xilinx platform as part of real time decision support for avionic applications. As experimental results, we compare the performance of two algorithms in terms of execution time and resource utilization. We showed that TimSort ranges from 1.07x to 1.16x faster than MergeSort when optimized hardware is used.

An Efficient Hardware Implementation of TimSort and MergeSort Algorithms Using High Level Synthesis

In today's world, sorting is a basic need and appropriate method starts with searching. Several sorting algorithms has been developed on CPU (Central Processing Unit). But according to current scenario, CPU is not so efficient in sorting. To get the more speedup of sorting algorithms parallelization should b e done. There are many ways of Parallelizing sorting methods which can be performed by using different tools. But for achieving high efficiency GPU (Graphics Processing Unit) comuting is the most preferable way. The authors of this paper surveyed various aspects in the direction of research of GPU based sorting algorithms. This paper also refined the different research gaps based on GPU sorting algorithms like parallel (Merge, Quick, Bitonic, Odd-Even, Count, and Radix etc.) by using GPU computing with CUDA (Compute Unified Device Architecture). Future re s e arch will motivate to do the work in GPU architecture.

A roadmap of parallel sorting algorithms using GPU computing

Recently, supercomputers structure and its software optimization have been popular subjects. Much of the software recently consumes a long period of time both to sort and search datasets, and thus optimizing these algorithms becomes a priority. In order to discover the most efficient sorting and searching algorithms for parallel processing units, one can compare CPU runtime as a performance index. In this paper, Quick, Bubble, and Merge sort algorithms have been chosen for comparison, as well as sequential and binary as search algorithms. Each one of the sort and search algorithms was tested in worst, average and best case scenarios. And each scenario was applied using multiple techniques (sequential, multithread, and parallel processing) on a various number of processors to spot differences and calculate speed up factor.The proposed solution aims to optimize the performance of a supercomputer focusing one-time efficiency; all tests were conducted by The IMAN1 supercomputer which is Jordan's first and fastest supercomputer.

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Parallel Processing of Sorting and Searching Algorithms Comparative Study

Sorting is a common problem in computer science. There are a lot of well- known sorting algorithms created for sequential execution on a single processor. Recently, many-core and multi-core platforms have enabled the creation of wide parallel algorithms. We have standard processors that consist of multiple cores and hardware accelerators, like the GPU. Graphic cards, with their parallel architecture, provide new opportunities to speed up many algorithms. In this paper, we describe the results from the implementation of a few dierent parallel sorting algorithms on GPU cards and multi-core processors. Then, a hybrid algorithm will be presented, consisting of parts executed on both platforms (a standard CPU and GPU). In recent literature about the implementation of sorting algorithms in the GPU, a fair comparison between many core and multi-core platforms is lacking. In most cases, these describe the resulting time of sorting algorithm executions on the GPU platform and a single CPU core.

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The comparison of parallel sorting algorithms implemented on different hardware platforms

Convolutional Neural Networks (CNNs) were created for image classification tasks. Quickly, they were applied to other domains, including Natural Language Processing (NLP). Nowadays, the solutions based on artificial intelligence appear on mobile devices and in embedded systems, which places constraints on, among others, the memory and power consumption. Due to CNNs memory and computing requirements, to map them to hardware they need to be compressed. This paper presents the results of compression of the efficient CNNs for sentiment analysis. The main steps involve pruning and quantization. The process of mapping the compressed network to FPGA and the results of this implementation are described. The conducted simulations showed that 5-bit width is enough to ensure no drop in accuracy when compared to the floating point version of the network. Additionally, the memory footprint was significantly reduced (between 85% and 93% comparing to the original model).

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Compression of Convolutional Neural Network for Natural Language Processing

This paper examines the performance of a Spatial Pooler (SP) of a Hierarchical Temporal Memory (HTM) in the task of noisy object recognition. To address this challenge, a dedicated custom-designed system based on the SP, histogram calculation module and SVM classifier was implemented. In addition to implementing their own version of HTM, the authors also designed a profiler which is capable of tracing all of the key parameters of the system. This was necessary, since an analysis and monitoring of the system performance turned out to be extremely difficult using conventional testing and debugging tools. 
The system was initially trained on artificially prepared videos without noise and then tested with a set of noisy video streams. This approach was intended to mimic a real life scenario where an agent or a system trained to deal with ideal objects faces a task of classifying distorted and noisy ones in its regular working conditions. 
The authors conduced a series of experiments for various macro parameters of HTM SP, as well as for different levels of video reduction ratios. The experiments allowed them to evaluate the performance of two different system setups (i.e. 'Multiple HTMs' and 'Single HTM') under various noise conditions with 32--frame video files. Results of all the tests were compared to SVM baseline setup. 
It was determined that the system featuring SP is capable of achieving approximately 12 times the noise reduction for a video signal with with distorted bits accounting for 13\% of the total. Furthermore, the system featuring SP performed better also in the experiments without a noise component and achieved a max F1 score of 0.96.

Noisy video classification with Spatial Pooler of Hierarchical Temporal Memory.

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Marcin Pietron

Papers

The comparison of parallel sorting algorithms implemented on different hardware platforms

Compression of Convolutional Neural Network for Natural Language Processing

Noisy video classification with Spatial Pooler of Hierarchical Temporal Memory.

Równoległa implementacja algorytmu winnowing dla operacji strumieniowej analizy tekstu