Asynchronous Circuit Design

Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications.

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A Designer's Guide to Asynchronous VLSI

An asynchronous pipeline style is introduced for high-speed applications, called MOUSETRAP. The pipeline uses standard transparent latches and static logic in its datapath, and small latch controllers consisting of only a single gate per pipeline stage. This simple structure is combined with an efficient and highly-concurrent event-driven protocol between adjacent stages. Post-layout SPICE simulations of a ten-stage pipeline with a 4-bit wide datapath indicate throughputs of 2.1-2.4 GHz in a 0.18-mum TSMC CMOS process. Similar results were obtained when the datapath width was extended to 16 bits. This performance is competitive even with that of wave pipelines, without the accompanying problems of complex timing and much design effort. Additionally, the new pipeline gracefully and robustly adapts to variable speed environments. The pipeline stages are extended to fork and join structures, to handle more complex system architectures.

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MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines

A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Cell circuit and layout with linear finfet structures

This volume originated from the 2002 Design, Automation and Test in Europe Conference and Exhibition, and examines computer hardware design and testing. It is aimed at researchers, professors, practitioners and students.

Proceedings : 2002 Design, Automation and Test in Europe, conference and exhibition : March 4-8, 2002, Paris, France

This work presents a back-end design flow for high performance asynchronous ASICs using single-track full-buffer (STFB) standard cells and industry standard CAD tools to perform schematic capture, simulation, layout, placement and routing. This flow is demonstrated and evaluated on a 64-bit asynchronous prefix adder and its test circuitry. The STFB standard cells provide low latency and fast cycle-times at the expense of some timing assumptions. This paper demonstrates that, by controlling top-block sizes and/or wire length within the place & route flow, ultra-high-performance circuits can be automatically designed. In particular, in the TSMC 0.25/spl mu/m process our post-layout STFB standard-cell 64-bit asynchronous prefix adder requires 0.96 mm/sup 2/, offers a latency of 2.1 ns, has a throughput of 1.4 GHz, and operates at five process corners as well as a wide-range of temperatures and voltages.

High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells

This paper presents a new fast and templatized family of fine-grain asynchronous pipeline stages based on the single-track protocol. No explicit control wires are required outside of the datapath and the data is 1-of-N encoded. With a forward latency of 2 transitions and a cycle time of 6 for most configurations, the new family can run at 1.6 GHz using MOSIS TSMC 0.25 /spl mu/m process. This is significantly faster than all known quasi-delay-insensitive templates and has less timing assumptions than the recently proposed ultra-high-speed GasP bundled-data circuits.

Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding

This paper presents a high-performance asynchronous template, single-track full-buffer (STFB), which achieves close to full-custom performance using a standard cell design flow and industry standard CAD tools to perform schematic capture, simulation, cell layout, and automatic placement and routing. This template and flow is demonstrated and evaluated with the implementation of a 64-bit asynchronous prefix adder, and its test circuitry, using the TSMC 0.25-/spl mu/m process. The 64-bit asynchronous prefix adder layout requires 0.96 mm/sup 2/ and the entire 260-k transistor test chip reaches a measured throughput of 1.45GHz. The design demonstrates that the STFB template can yield three times higher throughput with approximately half of the area of comparable quasi-delay-insensitive (QDI) templates, requires less timing assumptions than ultra-high-speed GasP bundled-data circuits, and can be designed with an automated place and route flow.

High performance asynchronous design using single-track full-buffer standard cells

In this paper, we propose a novel low swing driver using a Dynamic Diode-Connected Driver (DDCD) architecture. The receiver can be a simple inverter since the line swing is around Vdd/2 (from Vtn to Vdd- |Vtp|). The simulation results shows a reduction of the energy-delay product between 27% and 54% when compared with the full swing CMOS buffer for a 0.5µm and 0.18 µm process. Unlike most alternatives, no extra power supplies, nor a multi-threshold process, are required.

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Marcos Ferretti

Papers

A Designer's Guide to Asynchronous VLSI

High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells

Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding

High performance asynchronous design using single-track full-buffer standard cells

Low swing signaling using a dynamic diode-connected driver