Showing papers by "Marek Perkowski published in 1994"

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams

Abstract: An efficient package for construction of and operation on ordered Kronecker Functional Decision Diagrams (OKFDD) is presented. OKFDDs are a generalization of OBDDs and OFDDs and as such provide a more compact representation of the functions than either of the two decision diagrams. In this paper basic properties of OKFDDs and their efficient representation and manipulation are presented. Based on the comparison of the three decision diagrams for several benchmark functions, a 25% improve ment in size over OBDDs is observed for OKFDDs.

Programmable analog array circuit

Abstract: There is disclosed a programmable analog or mixed analog/digital circuit. More particularly, this invention provides a circuit architecture that is flexible for a programmable electronic hardware device or for an analog circuit whose input and output signals are analog or multi-valued in nature, and primarily continuous in time. There is further disclosed a design for a current-mode integrator and sample-and-hold circuit, based upon Miller effect.

A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays

Abstract: This paper introduces a new design approach that combines logic and layout synthesis for Cellular-Architecture (CA) FPGAs. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly-shaped multi-level structure of (mostly) locally connected cells. This two-dimensional array of logic cells is well suited for CA-type FPGA realization. Two stages: restricted factorization and technology folding are discussed in more details. The architecture constraints and the implementation are presented for ATMEL6000 series architecture.

A field programmable analog array for continuous, fuzzy, and multi-valued logic applications

Abstract: We propose a novel approach to the realization of continuous, fuzzy, and multi-valued logic (mvl) circuits. We demonstrate how a general-purpose field programmable analog array (FPAA), with cells realizing simple arithmetic operations on signals, can be used for this purpose. The FPAA, which is being implemented in a bipolar transistor array technology, operates from /spl plusmn/3.3 V or /spl plusmn/5 V power supplies and works in the range of frequencies up to several hundred MHz. >

Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping

Abstract: This paper introduces the concepts of PseudoKronecker Decision Diagrams (PKDDs) with Negated Edges, as well as F+ee Kronecker Decision Diagrams (FKDDs), that generalize both the well-known Binary Decision Diagmms and Functional Decision Diagmms, as well as Ihe recently introduced Ordered Kronecker Decision Diagrams (OKDDs . We give efficient algorithm for Ihe generation / o FKDDs for multi-output functions and show their application 20 FPGA mapping. On MCNC benchmarks we demon&ale Ihe advantage of FKDDs in terms of reduced number.9 of nodes (cells) and levels in Ihe circuit over Ihe OKDDs and Permuted RM ties. The mapping algorithm can be easily adopied lo other cellular FPGAS, especially those from Motorola.

Multiple-valued-input TANT networks

Abstract: The paper proposes mvTANTs, three-level networks with multiple-valued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks with True Inputs). One of possible interpretations of mvTANT is a four-level binary network with input decoders which realize multiple-valued literals. Similar to mvPLAs, mvTANTs have regular structures with predictable timing. Compared with mvPLAs, however, they have at least 25% less input wires to the third-level (NAND) plane and not more outputs from the second-level (AND) plane than the mvPLA. Thus, in many cases they have less gates and connections, and are useful to minimize Boolean functions in cellular FPGAs and other regular structures. >

An exact solution to the fitting problem in the application specific state machine device

Abstract: In this paper the fitting problem for a new Application Specific State Machine Device, CY7C361, from Cypress Semiconductor is formulated and the solution is proposed. This fitting problem consists of mapping a netlist obtained from high-level synthesis into the chip’s physical resources. In general, a mapping (fitting) problem can be formulated as one of the labeled graph isomorphism between the netlist graph and the subgraph of the resources graph. However, the specific architecture-related constraints of the CY7C361 device cause the fitting problem to be generalized as a graph isomorphism problem with some additional mapping constraints and node multiplication (placing some nodes of the netlist graph in more than one node of the physical graph). Such formulation is quite general for a class of Complex Programmable Logic Device (CPLD) fitting problems, and has not been found in the literature. We implemented an exact, constraint-based, tree searching algorithm with several kinds of backtracking.

for a Field-Programmable Analog Array

Abstract: The AN10E40 brings to analog what FPGAs brought to digital; extremely rapid production and prototype circuit realization with field re-programmability. The AN10E40 consists of a 4 x 5 matrix of fully configurable switched capacitor cells, enmeshed in a fabric of programmable interconnect resources. These programmable features are directed by an on-chip SRAM configuration memory. The SRAM configuration memory is initialized on power up via an off chip serial PROM or through the AN10E40’s standard microprocessor peripheral interface. A configuration memory image is easily constructed using the companion AnadigmDesigner software which includes an extensive library of adjustable, proven, pre-built functions. The configurable analog blocks are often consumed one at a time, though some of the more complex library functions may consume two or more blocks. Specialized IO cells surround the core to bring your analog signals in and out of the array. The AN10E40 coupled with the intuitive AnadigmDesigner software gives both digital and analog designers a competitive advantage in designing analog circuits that can’t really be compared to any other design system in existence. Quickly constructed, accurate, drift free, temperature compensated and programmable analog circuits are now yours. Imagine the power of programmable with the versatility of analog. Benefits • Extremely Rapid Analog Design – Minutes not weeks to re-spin a new design idea • In Circuit Programmable – Behavior can be changed as fast as 125 microseconds • Re-Configurable Using Conventional Logic, Serial PROMs or Microcontrollers • Extremely Stable over Voltage and Temperature • No Component Aging • Reliable and Repeatable Performance • Flexible Internal Clock and Routing Resources • No More Trimming Components • No More Tuning Components AN10E40