Marion G. Harmon

TL;DR: This paper describes an approach for bounding the worst and best case performance of large code segments on machines that exploit both pipelining and instruction caching and indicates that the timing analyzer efficiently produces tight predictions of best and best-case performance for pipelined and instruction cache.

TL;DR: In this paper, a static cache sitnula- tion is used to analyze a program's control flow to stati- cally categorize the caching behavior of each instruction and then a timing analyzer, which uses the Categorization informa- tion, then estimates the worst-case instruction cache per- formance for each loop and function in the program.

TL;DR: This paper describes an approach for bounding the worst-case performance of large code segments on machines that exploit both pipelining and instruction caching, and a graphical user interface is invoked that allows a user to request timing predictions on portions of the program.

TL;DR: Results of incorporating instruction cache predictions within pipeline simulation show that timing predictions for set-associative caches remain just as tight as predictions for direct-mapped caches.

TL;DR: A novel technique for predicting point-to-point execution times on contemporary microprocessors is presented, which uses machine-description rules, similar to those that have proven useful for code generation and peephole optimization, to translate compiled object code into a sequence of very low-level instructions.