An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

A method for fabricating a semiconductor device, in which a lifting phenomenon can be prevented from occurring in forming an amorphous carbon film on an etched layer having tensile stress. According to the invention, since a compression stress on the etched layer or the amorphous carbon film can be reduced or a compression stress film is formed between the etched layer or the amorphous carbon film to prevent a lifting phenomenon from occurring and thus another pattern can be formed to fabricate a highly integrated semiconductor device.

Method for Fabricating Semiconductor Device

A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

Silicide contacts having different shapes on regions of a semiconductor device

Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example.

Method of forming pitch multipled contacts

A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer ( 26 ) formed over a substrate ( 11 ), thereby forming etched gates ( 62, 64 ) having vertical sidewall profiles ( 61, 63 ). While a blanket nitrogen implant ( 46 ) of the intrinsic polysilicon layer ( 26 ) may occur prior to gate etch, more idealized vertical gate sidewall profiles ( 61, 63 ) are obtained by fully doping the gates ( 80, 100 ) during the source/drain implantation steps ( 71, 77, 91, 97 ) and after the gate etch.

Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

Non-volatile memory (nvm) and logic integration

A method of making a logic transistor in a logic region of a substrate and a non-volatile memory cell in an NVM region of the substrate includes forming a gate dielectric layer on the substrate. A first polysilicon layer is formed on the gate dielectric. The first polysilicon layer is formed over the NVM region and removing the first polysilicon layer over the logic region. A dielectric layer is formed over the NVM region including the first polysilicon layer and over the logic region. A protective layer is formed over the dielectric layer. The dielectric layer and the protective layer are removed from the logic region to leave a remaining portion of the dielectric layer and a remaining portion of the protective layer over the NVM region. A high-k dielectric layer is formed over the logic region and the remaining portion of the protective layer. A first metal layer is formed over the high K dielectric layer. The first metal layer, the high K dielectric, and the remaining portion of the protective layer are removed over the NVM region to leave a remaining portion of the first metal layer and a remaining portion of the high K dielectric layer over the logic region. A conductive layer is deposited over the remaining portion of the dielectric layer and over the first metal layer. The NVM cell and the logic transistor are formed and this includes patterning the conductive layer.

Non-volatile memory and logic circuit process integration

A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

Mark D. Hall

Papers

Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility

Non-volatile memory (nvm) and logic integration

Non-volatile memory and logic circuit process integration

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

Method of making a logic transistor and a non-volatile memory (nvm) cell