Patent
Non-volatile memory (nvm) and logic integration
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TLDR
In this article, a method of forming an NVM cell and a logic transistor using a semiconductor substrate was proposed, where a polysilicon dummy gate was replaced by a metal gate.Abstract:
A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.read more
Citations
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Patent
Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology
TL;DR: In this paper, a gate structure is formed over the logic portion comprising a high k dielectric and a metal gate, which is then removed from the logic part leaving a portion of the second layer over the control gate and the select gate.
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TL;DR: In this article, a thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region.
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Method of making a logic transistor and a non-volatile memory (nvm) cell
Mehul D. Shroff,Mark D. Hall +1 more
TL;DR: In this article, a method of forming a semiconductor device includes forming a gate layer over a substrate in the NVM region and the logic region, forming an opening in the first gate layer, forming a charge storage layer in the opening, and replacing the first patterned gate layer portion with a logic gate comprising metal.
References
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Journal ArticleDOI
Metal nanocrystal memories. I. Device design and fabrication
TL;DR: In this article, the design principles and fabrication process of metal nanocrystal memories are described, and one-dimensional (1-D) analyses are provided to illustrate the concept of work function engineering, both in direct tunneling and F-Ntunneling regimes.
Patent
Semiconductor integrated circuit device and a method of manufacturing the same
TL;DR: In this paper, a semiconductor device including a memory cell including a first gate insulating film over the semiconductor substrate, a control gate electrode over the first gate and a memory gate over the second gate, with the first and second semiconductor regions in the substrate positioned on a gate electrode side and memory gate side, respectively, respectively.
Patent
Nonvolatile semiconductor memory device
TL;DR: In this paper, a nonvolatile semiconductor memory device which can enhance a stable control of a voltage applied to a memory cell and has excellent capability of controlling a drain voltage is presented.
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Semiconductor integrated circuit and nonvolatile memory element
TL;DR: In this article, a semiconductor integrated circuit device is provided on a polycrystalline substrate, and includes a plurality of word lines, data lines, and an electrically programmable and erasable non-volatile memory cells respectively coupled to the plurality of words and data lines.
Patent
Process for manufacturing dual work function metal gates in a microelectronics device
TL;DR: In this article, the authors presented a method of forming a dual work function metal gate microelectronics device using stacked gate structures, which includes removing the sacrificial gate layer in at least one of the nMOS or pMOS stacked gate structure, thereby forming a gate opening 825.