Advances in VLSI have resulted in more and more complex circuitry, fueling the need for programs that analyze IC mask artwork. This article describes Goalie, an artwork analysis system, by explaining the algorithms used to support circuit extraction, Boolean geometric operations, connectivity analysis, capacitance measurement and design checking. Tests on several systems have shown that Goalie runs at least as fast as algorithms currently in use, but it requires less main memory, so large layouts can be handled on small computers, or even on personal workstations.

Goalie: A Space Efficient System for VLSI Artwork Analysis

Formal hardware verification ranges from proving that two combinational circuits compute the same functions to the much more ambitious task of proving that a sequential circuit obeys some abstract property expressed in temporal logic. In tracing the history of work in this area, we find a few efforts in the 1970s and 1980s, with a big increase in verification capabilities the late 1980s up through today. The advent of efficient Boolean inference methods, starting with Binary Decision Diagrams (BDDs) and more recently with efficient Boolean satisfiabiIity (SAT) checkers has provided the enabling technology for these advances.

The Best of ICCAD

An integrated design system (IDS) for handcrafted digital VLSI circuits is presented. Developed over a two-year period, IDS consists of both in-house and third-party software, integrated with a hierarchical top-down design methodology. A key component of IDS is the Structured LAyout VErification (SLAVE) program for electrical verification of mask artwork. Implementation of a top-down design methodology allows SLAVE to use the separate hierarchical representations in the logic, circuit, and layout models to completely verify the connectivity of the mask layout. SLAVE has been successfully adapted to both bipolar and CMOS technologies; it provides error detection down to specific signal nets and device nodes and is extremely fast. SLAVE typically runs under 70 min on a VAX 11/780 for a complex IC containing up to 50K discrete devices and is modeled using six levels of hierarchical nesting.

An integrated approach for hierarchical verification of VLSI mask artwork

The author presents the program HEXDRC for hierarchical circuit extraction and design rule check. The main problem for hierarchical layout verification is to handle interactions between different cells effectively. The kind of interactions however strongly depends on the actual design style, so that it will be impossible to find a solution which will work optimal for all layouts. To solve this problem, HEXDRC offers a lot of possibilities to modify the implemented basic algorithm by user instructions. HEXDRC includes design rule checking and netlist extraction, both working on the same database. This allows to verify more complex rules than with separate tools. The author discusses the basic concept, describes how to adapt the program to a special design style and presents first experimental results. >

Hierarchical layout verification for submicron designs

This paper describes a set of heuristics for a hierarchical circuit extractor. The strength of these algorithms lies in their capability for fully exploiting the natural hierarchical structure of IC layouts, and in handling overlapping cell instances without creating partial devices. Technology independence is implemented by keeping all technology dependent information in a user accessible file external to the program, which is also used to define the extent of parameter extraction. Circuit extraction is performed in a bottom-up manner and produces a netlist description with the same hierarchical structure as the layout.

A Technology Independent Approach to Hierarchical IC Layout Extraction

HEX is a general purpose geometric feature extractor with an integrated circuit layout emphasis. It differs from previous extractors in that it is process-independent and has the ability to do a simple or detailed extraction of circuit features depending on a user-provided sequence of instructions. Internally the extraction process is carried out by an "instruction engine". The extractor produces an output graph showing feature connectivity and attaches extracted attributes to the feature nodes. In circuit applications the post-processed output is suitable for detailed simulation. HEX is currently in use at Siemens Corporation, West Germany.

Mark Hofmann

Papers

HEX: An Instruction-Driven Approach to Feature Extraction