A programmable integrated circuit capacitor array includes a plurality of binarily weighted capacitors (16) and a plurality of switches (18) selectively coupling the capacitors in parallel between first and second terminals. A control circuit (10) responds to a plurality of capacitance selection inputs (CS0,1,2) in conjunction with a plurality of trim inputs (TR0,1) and a sign input (TRS) to produce a plurality of selection signals (SEL0,1...7) on control electrodes of the switches to couple one or more of the capacitors and thereby provide an accurate value of the desired capacitance between the first and second terminals despite any manufacturing deviations in capacitance per unit area.

Capacitor array having user-adjustable, manufacturer-trimmable capacitance and method

A sample and hold inductor current sense configuration senses inductor current flowing through an output inductor of a voltage regulator and generates an average of the sensed inductor current. The average of the sensed inductor current may be generated from samples of peaks and valleys of the sensed inductor current. For example, the peak of the sensed inductor current may be stored in a first capacitor and the valley of the sensed inductor current may be stored in a second capacitor. The first and second capacitors may be coupled together to generate the average of the sensed inductor current. The average of the sensed inductor current may be provided to a droop control circuit to control droop of an output voltage of the voltage regulator. An input offset voltage of a current sense amplifier sensing the inductor current may be calibrated between samplings of the sensed inductor current.

Sample and hold technique for generating an average of sensed inductor current in voltage regulators

A voltage regulator may be configured to detect variation in load current and control transient response when the load current has a high slew rate or varies at high repetition rates. A linear control circuit may be employed to control charging of an output capacitor and a load of the regulator. Upon detection of high load current step-up change at high slew rates, a non-linear control circuit may be activated. The fast load current step change may be detected by comparing an output voltage of the regulator to a feedback input of an error amplifier of the linear control circuit. The output of the error amplifier may be clamped to prevent output voltage ring-back when using the non-linear control circuit or to control load release dip. Output voltage overshoot may be controlled by turning OFF a top switch that charges the output capacitor before the inductor current becomes zero.

Non-linear control techniques for improving transient response to load current step change

An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Analog to digital converter with dither

An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance means and switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Gain error correction in an analog-to-digital converter

A charge redistribution analog-to-digital converter. This converter includes an offset correcting circuit operatively connected in parallel with a capacitor array and responsive to a sampling input of the analog-to-digital converter, and a gain correcting circuit operatively connected in parallel with a sampling capacitor and responsive to the sampling input of the analog-to-digital converter. In another general aspect, an analog-to-digital converter calibration method for a charge redistribution analog-to-digital converter, that includes adjusting an input offset of an input of the analog-to-digital converter and adjusting a gain offset of the analog-to-digital converter. The steps of adjusting are then repeated until a predetermined level of error is achieved for the analog-to-digital converter.

Martin G. Cotter

Papers

Charge redistribution analog-to-digital converter with system calibration