The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.

https://www.mdpi.com/2079-9292/8/10/1116/pdf

A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

Real-time Hardware-In-the-Loop (HIL) simulation tools used at various levels in the development of modern power electronics are inevitable, either testing the control board implementations with signal-level simulators or validating the power converters with power HIL solutions. The high computational power of FPGA devices used in HIL tools offers many advantages, but the developers have to make a trade-off between the precision of HIL models and the resources required by the realization. The half-bridge is the building block of many power converters, its efficient real-time model is useful in the development of HIL simulators of more complex systems. In this paper the advantages and disadvantages of real-time models of the half-bridge are studied. The simple switching function model, the more complex but widely used Associated Discrete Circuit (ADC) model, and a PI controller based model with enhanced Discontinuous Conduction Mode (DCM) emulation are compared.

Power Converter Half-bridge Models in the Light of Real-time FPGA Implementation

The advances in FPGA technology have enabled to develop fast HIL (Hardware-in-the-Loop) simulators, revolutionizing control software and hardware development for power electronics. HIL simulators should reproduce the same analogue signals that could be measured on real main circuits. A very common limitation in these applications is the usable pin count of the FPGA, therefore using the most pin-effective Digital-to-Analogue Converters (DACs) becomes critical. $\Sigma-\Delta$ DACs provide a simple, FPGA-synthesizable solution using a single pin for each output, but the output signal's bandwidth and latency is usually not sufficient, because of the required analogue filters. Higher order $\Sigma-\Delta$ DACs usually perform much better in the aspect of the Signal-to-Noise-Ratio (SNR) but not the usable bandwidth. This paper introduces a new bitstream DAC architecture based on the sliding mode control of the output analogue filter model. It is optimized mainly to reproduce current transducer signals in power electronics (usually triangle waves), which can be done more accurately than traditional $\Sigma-\Delta$ solutions.

Marton Hegedus

Papers

FPGA-Driven DAC with Second Order Sliding Mode Control of Filter Model for Hardware-In-the-Loop Simulators