System-on-Chip (SoC) complexity and the increasing costs of silicon motivate the breaking of an SoC into smaller "chiplets." A chiplet-based SoC design process has the promise to enable fast SoC construction by using advanced packaging technologies to tightly integrate multiple disparate chips (e.g., CPU, GPU, memory, FPGA). However, when assembling chiplets into a single SoC, correctness validation becomes a significant challenge. In particular, the network-on-chip (NoC) used within the individual chiplets and across chiplets to tie them together can easily have deadlocks, especially if each chip is designed in isolation. We introduce a simple, modular, yet elegant methodology for ensuring deadlock-free routing in multi-chiplet systems. As an example, we focus on future systems combining chiplets on an active silicon interposer. To maximize modularity, each individual chiplet is free to implement its own NoC topology and local routing algorithm, and the interposer can implement its own independent topology and routing. Our methodology imposes a few simple turn restrictions applied only to traffic as it flows into or out of the chiplets from the interposer, and we provide a way to determine these restrictions. The end result is an overall approach that enables highly-modular, chiplet-based SoC construction while eliminating deadlocks with high performance.

Modular routing design for chiplet-based systems

Reliability is one of the most challenging problems in the context of three-dimensional network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the manufacturing process in order to prevent costly redesigns of a target system. This article classifies the potential physical faults of a baseline TSV-based 3D NoC architecture by targeting two-dimensional (2D) NoC components and their inter-die connections. In this paper, through-silicon via (TSV) issues, thermal concerns, and single event effect (SEE) are investigated and categorized, in order to propose evaluation metrics for inspecting the resiliency of 3D NoC designs. A reliability analysis for major source of faults is reported in this article separately based on their mean time to failure (MTTF). TSV failure probability induced by inductive and capacitive coupling is also discussed. Finally, the paper provides a formal reliability analysis on the aggregated faults that affect TSV. This formal analysis is critical for estimating the resiliency of different components in order to mitigate the redundancy cost of fault-tolerant design or to examine the efficiency of any proposed fault-tolerant methods for 3D NoC architectures.

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

NoC routing protocols – objective-based classification

Three-dimensional (3D) Network-on-Chip (NoC) is an emerging technology that has the potential to achieve high performance with low power consumption for multicore chips. However, to fully realize their potential, we need to consider novel 3D NoC architectures. In this paper, inspired by the inherent advantages of small-world (SW) 2D NoCs, we explore the design space of SW network-based 3D NoC architectures. We leverage machine learning to intelligently explore the design space to optimize the placement of both planar and vertical communication links for energy efficiency. We demonstrate that the optimized 3D SW NoC designs perform significantly better than their 3D MESH counterparts. On an average, the 3D SW NoC shows 35% energy-delay-product (EDP) improvement over 3D MESH for the nine PARSEC and SPLASH2 benchmarks considered in this work. The highest performance improvement of 43% was achieved for RADIX. Interestingly, even after reducing the number of vertical links by 50%, the optimized 3D SW NoC performs 25% better than the fully connected 3D MESH, which is a strong indication of the effectiveness of our optimization methodology.

Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach

3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$ improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is light-weight and has only one virtual channel along the $Y$ dimension.

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A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs

In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases.

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs

In this paper, we detail the design and implementation of a router for vertically-partially-connected 3D-NoCs based on stacked 2D-meshes. This router implements the necessary hardware to support a recently introduced routing algorithm called "Elevator-First", which targets topologies with irregularly placed vertical connections in a deadlock free manner, using only two virtual channels in the plane. The micro-architectural design shows that the proposed router requires few additional hardware. Our studies about the practicality of the algorithm and its router implementation demonstrate that it has low overhead compared to a router for fully connected 3D-NoCs. Using ST Microelectronics 65nm CMOS technology Elevator-First router with 7 ports has a total area of 0.07mm², an Operating frequency of over 3GHz and a power consumption of around 3mW.

A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies

In this paper we present the basic ideas behind the development of our novel ring based network-on-chip (NoC) architecture, called ldquoCoronardquo. To achieve minimum hop count, shortest path routing has been applied. Consequently, this ends in average latency reduction (averagely 45%). NS-2 tool is utilized to estimate average latency and packet drop in Corona and 2D mesh with localized and non-localized traffic scenarios. The power consumption of Corona and 2D mesh have been analyzed with LUNA framework. Also, the power consumption is reduced averagely in Corona in comparison to 2D mesh 21% and 29% for localized and non-localized traffic scenarios.

Corona: Ring-based interconnected topology for on-chip network

NoC is a potent solution to address design complexity and productivity problems whose its key component is the interconnect architecture which directly affects both cost and performance parameters. The purpose of this paper is to present the basic ideas behind the development of our new hierarchical network-on-chip (NoC) architecture, called ldquoNormardquo that its most distinguished characteristic is its hierarchical nature. We present two types of Norma, Norma-I and Norma-II which have been compared to 2D Mesh. Results illustrate that Norma-I and Norma-II have far more proper functionality than 2D Mesh, when 75 percent of whole traffic interacts in each subnet.

Norma: A hierarchical interconnection architecture for Network on Chip

Network infrastructure today has become highly evolved and is required to support converged IP applications such as the triple play of video, voice and data. All of these applications have numerous means of implementation and myriad protocols. More emphasis on quality is being placed on communications equipment manufacturers and network providers alike to provide high quality user experience for applications such as IPTV and VoIP. One of the solutions is the Metro Ethernet network. In this paper, we present the results of the first phase of the Iran Telecommunication Research Center Broadband Ethernet Simulation (ITRC-BES) project which is defined by Iran Telecommunication Research Center Next Generation Network (ITRC-NGN) Group based on the Data Communication of IRAN Organization Network (DCI) requirements. We analyze performance parameters of both VoIP and IPTV traffic flows in a selected hybrid topology with OPNET. This topology contains RPR layer 2 rings called regions which are connected with each other by the IP/MPLS layer 3 routers. VPLS is configured in the network among interactive regions and both IPTV and VoIP traffic are assigned to the appropriate LSPs. Results show that QoS and service differentiation configuration in such a network are necessary topics. In addition, although, QoS mechanism can improve the quality of VoIP, the IPTV flows quality is significantly decreased by the adding more than 300 IPTV users to the network.

Maryam Bahmani

Papers

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs

A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies

Corona: Ring-based interconnected topology for on-chip network

Norma: A hierarchical interconnection architecture for Network on Chip

Improvement of VoIP QoS parameters in comparison to IPTV requirements in Next Generation Broadband Ethernet network