To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. In this paper, we first provide a general description of NoC architectures and applications. Then, we enumerate several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, we address the interactions among these research problems and put the NoC design process into perspective.

Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

In this paper we present a reconfigurable routing algorithm for a 2D-mesh network-on-chip (NoC) dedicated to fault- tolerant, massively parallel multi-processors systems on chip (MP2-SoC). The routing algorithm can be dynamically reconfigured, to adapt to the modification of the micro-network topology caused by a faulty router. This algorithm has been implemented in a reconfigurable version of the DSPIN micro-network, and evaluated from the point of view of performance (penalty on the network saturation threshold), and cost (extra silicon area occupied by the reconfigurable version of the router).

/pdf/a-reconfigurable-routing-algorithm-for-a-fault-tolerant-2d-1r0vyhd8pi.pdf

A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip

https://si2.epfl.ch/%7Edemichel/publications/archive/2008/Network_on_chip_design_and_synthesis_outlook_41_3.pdf

Invited paper: Network-on-Chip design and synthesis outlook

In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases.

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs

The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture DSPIN is a scalable packet switching micro-network dedicated to GALS (Globally Asynchronous, Locally Synchronous) clustered, multi-processors, systems on chip The DSPIN architecture has a very small foot-print and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area This article describes two approaches to implementing a distributed NoC in a GALS environment

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures This book includes contributions from high level international teams working in this field

3D Integration for NoC-based SoC Architectures

In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi Processors System on Chip. The 5 relevant parameters are Silicon Area, Network Saturation Threshold, Communication Throughput, Packet Latency and Power Consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.

/pdf/systematic-comparison-between-the-asynchronous-and-the-multi-4994zbzzq7.pdf

Abbas Sheibanyrad

Papers

Elevator-First: A Deadlock-Free Distributed Routing Algorithm for Vertically Partially Connected 3D-NoCs

A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach

Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

3D Integration for NoC-based SoC Architectures

Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture