A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode disposed on the substrate, a gate dielectric layer disposed on the substrate and the gate electrode, an oxide semiconductor pattern disposed on the gate dielectric layer, a first insulating pattern disposed on the oxide semiconductor pattern that overlaps the gate electrode, a second insulating pattern disposed on the oxide semiconductor pattern and spaced apart from the first insulating pattern, source and drain electrodes spaced apart from each other on the oxide semiconductor pattern, a pixel electrode pattern disposed on the second insulating pattern to make contact with the source electrode, and a channel area defined where the oxide semiconductor pattern overlaps the gate electrode. A high carrier mobility channel is formed in the channel area when a turn-on voltage is applied to the gate electrode.

Display apparatus and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a gate electrode as formed over a surface of the substrate with a gate dielectric film interposed therebetween, source/drain layers formed in said semiconductor substrate to oppose each other with a channel region residing between these layers at a location beneath the gate electrode, the source/drain layers each having a low resistivity region and an extension region being formed to extend from this low resistivity region toward the channel region side and being lower in impurity concentration and shallower in depth than the low resistivity region, a first impurity-doped layer of a first conductivity type formed in the channel region between the source/drain layers, a second impurity-doped layer of a second conductivity type formed under the first impurity-doped layer, and a third impurity-doped layer of the first conductivity type formed under the second impurity-doped layer, wherein the first impurity-doped layer is equal or less in junction depth than the extension regions of the source/drain layers whereas the second impurity-doped layer is designed in impurity concentration and thickness to be fully depleted due to a built-in potential as created between the first and third impurity-doped layers.

Semiconductor device and method of fabricating the same

By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.

Self-biasing transistor structure and an SRAM cell having less than six transistors

Low voltage, middle voltage and high voltage CMOS devices have upper buffer layers of the same conductivity type as the sources and drains that extend under the sources and drains and the gates but not past the middle of the gates, and lower bulk buffer layers of the opposite conductivity type to the upper buffer layers extend from under the upper buffer layers to past the middle of the gates forming an overlap of the two bulk buffer layers under the gates. The upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers. For middle voltage and high voltage devices the upper buffer layers together with the lower bulk buffer layers provide a resurf region.

Short channel lv, mv, and hv cmos devices

A Fermi-FET includes a drain field termination region between the source and drain regions, to reduce and preferably prevent injection of carriers from the source region into the channel as a result of drain bias. The drain field terminating region prevents excessive drain induced barrier lowering while still allowing low vertical field in the channel. The drain field terminating region is preferably embodied by a buried counterdoped layer between the source and drain regions, extending beneath the substrate surface from the source region to the drain region. The buried counterdoped layer may be formed using a three tub structure which produces three layers between the spaced apart source and drain regions. The drain field terminating region may also be used in a conventional MOSFET. The channel region is preferably formed by epitaxial deposition, so that the channel region need not be counterdoped relative to the drain field terminating region. Higher carrier mobility in the channel may thereby be obtained for a given doping level.

Methods of fabricating short channel fermi-threshold field effect transistors including drain field termination region

A semiconductor device includes a substrate having a first conduction type. A gate insulating film is provided on the substrate. A gate electrode is formed on the gate insulating film. A source region provided on the substrate has a second conduction type different from the first conduction type. A drain region provided on the substrate has the second conduction type. The source region and the drain region extend below the gate insulating film, and are located at respective sides of the gate electrode. A first region provided on the substrate has the first conduction type and extends below the gate insulating film. A second region provided on the substrate has the second conduction type, and extends below the first region. The second region connects with the first region via a pn junction. Third regions provided on the substrate have the first conduction type, and connect with the second region via respective pn junctions. A first one of the third regions extends between the second region and the source region. A second one of the third regions extends between the second region and the drain region. The first region has a width which is smaller than a sum of a width of a depletion layer caused by the pn junction with the second region and a width of a depletion layer caused by application of a voltage to the gate electrode. Third regions have a width which is greater than a sum of a width of a depletion layer caused by the source region and a width of a depletion layer caused by the pn junctions with the second region.

Method of manufacturing transistor with channel implant

A semiconductor device includes a substrate having a first conduction type. A gate insulating film is provided on the substrate. A gate electrode is formed on the gate insulating film. A source region provided on the substrate has a second conduction type different from the first conduction type. A drain region provided on the substrate has the second conduction type. The source region and the drain region extend below the gate insulating film, and are located at respective sides of the gate electrode. A first region provided on the substrate has the first conduction type and extends below the gate insulating film. A second region provided on the substrate has the second conduction type, and extends below the first region. The second region connects with the first region via a pn junction. Third regions provided on the substrate have the first conduction type, and connect with the second region via respective pn junctions. A first one of the third regions extends between the second region and the source region. A second one of the third regions extends between the second region and the drain region. The first region has a depth-direction width which is smaller than a sum of a depth-direction width of a depletion layer caused by the pn junction with the second region and a depth-direction width of a depletion layer caused by application of a voltage to the gate electrode. Third regions have a lateral-direction width which is greater than a sum of a lateral-direction width of a depletion layer caused by the source region and a lateral-direction width of a depletion layer caused by the pn junctions with the second region.

Masaki Funaki

Papers

Method of manufacturing transistor with channel implant

MOSFET device having depletion layer