Patent
Method of manufacturing transistor with channel implant
TLDR
In this article, a gate insulating film is provided on the substrate and a gate electrode is formed on the gate-insulating film, and the drain region connects with the first region via a pn junction.Abstract:
A semiconductor device includes a substrate having a first conduction type. A gate insulating film is provided on the substrate. A gate electrode is formed on the gate insulating film. A source region provided on the substrate has a second conduction type different from the first conduction type. A drain region provided on the substrate has the second conduction type. The source region and the drain region extend below the gate insulating film, and are located at respective sides of the gate electrode. A first region provided on the substrate has the first conduction type and extends below the gate insulating film. A second region provided on the substrate has the second conduction type, and extends below the first region. The second region connects with the first region via a pn junction. Third regions provided on the substrate have the first conduction type, and connect with the second region via respective pn junctions. A first one of the third regions extends between the second region and the source region. A second one of the third regions extends between the second region and the drain region. The first region has a width which is smaller than a sum of a width of a depletion layer caused by the pn junction with the second region and a width of a depletion layer caused by application of a voltage to the gate electrode. Third regions have a width which is greater than a sum of a width of a depletion layer caused by the source region and a width of a depletion layer caused by the pn junctions with the second region.read more
Citations
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Patent
Semiconductor device and method of fabricating the same
TL;DR: In this paper, a channel region is created between the source and drain layers of a semiconductor substrate to oppose each other with a built-in potential between the first and third impurity-doped layers, where the second impurity layer is designed in impurity concentration and thickness to be fully depleted.
Patent
Self-biasing transistor structure and an SRAM cell having less than six transistors
TL;DR: In this article, a self-biasing semiconductor switch is provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements.
Patent
Short channel lv, mv, and hv cmos devices
TL;DR: In this article, the upper buffer layers and the lower bulk buffer layers can be implanted for both the NMOS and PMOS FETs using two masking layers, and they provide a resurf region for middle voltage and high voltage devices.
Patent
Method of making a self-aligned silicide
TL;DR: In this paper, a self-aligned silicide which has an impurity diffusion region in a lower part of the source/drain regions adjacent to the isolating region is made, resulting in more surface area for the formation of a wide border contact window.
Patent
Semiconductor memory device and fabrication thereof
TL;DR: In this paper, a semiconductor memory device comprising a substrate of a first conductivity type, a plurality of first diffusion regions in which atoms of a second dopant opposite to the firstconductivity type are diffused, the second diffusion regions being disposed in the substrate and spaced one after another to define a channel between two adjacent first-and second-dope diffusion regions, and gate oxide regions on the channels, where two adjacent second-and third-dopant regions cover two side surface portions of each of the first-layer diffusion regions with a lower surface portion of
References
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Patent
MOSFET with reduced short channel effect
TL;DR: In this paper, a gate-insulating MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate and a channel region sandwiched between the source and the drain regions and made up of a first layer and a second layer is disclosed.
Patent
Process for manufacturing CMOS integrated devices with reduced gate lengths
TL;DR: In this article, a process for manufacturing CMOS integrated devices with gate lengths of less than one micron and high supply voltage is described, where less doped source and drain regions are provided in only one of the two MOS transistors, e.g. in the N-channel transistor, to increase the breakdown voltage.
Patent
Field effect transistor structure and method
TL;DR: In this paper, a gate electrode is implanted into the substrate and a thin oxide layer is formed over the device, followed by an implant of a second lightly doped drain region and an anisotropic etch back to form sidewall regions alongside the gate electrode.
Patent
Method for making an LDD MOSFET with a shifted buried layer and a blocking region
Kit M Cham,Paul Vande Voorde +1 more
TL;DR: In this article, a MOSFET structure characterized by a lightly doped tip region located between the channel and drain, and a buried region located below the tip region and shifted laterally towards the drain was proposed.
Patent
Method of manufacturing a floating gate type nonvolatile memory cell having an offset region
TL;DR: In this article, a floating gate type nonvolatile memory cell has an offset region, where the length of the offset region is defined by the portion of the substrate covered by the injection blocking film formed on the side wall of the floating gate electrode.