A lighting device comprising first and second groups of solid state light emitters, which emit light having peak wavelength in ranges of from 430 nm to 480 nm, and first and second groups of lumiphors which emit light having dominant wavelength in the range of from 555 nm to 585 nm. In some embodiments, if current is supplied to a power line, a combination of (1) light exiting the lighting device which was emitted by the first group of emitters, and (2) light exiting the lighting device which was emitted by the first group of lumiphors would have a correlated color temperature which differs by at least 50 K from a correlated color temperature which would be emitted by a combination of (3) light exiting the lighting device which was emitted by the second group of emitters, and (4) light exiting the lighting device which was emitted by the second group of lumiphors.

Lighting device and lighting method

A light emitting die package includes a substrate, a reflector plate, and a lens. The substrate has traces for connecting an external electrical power source to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad, and includes a reflective surface to direct light from the LED in a desired direction. The lens is free to move relative to the reflector plate and is capable of being raised or lowered by the encapsulant that wets and adheres to it and is placed at an optimal distance from the LED chip(s). Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink).

Power surface mount light emitting die package

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

An LED illumination apparatus according to the present invention includes at least one connector and a lighting drive circuit. The connector is connected to an insertable and removable card-type LED illumination source, which includes multiple LEDs that have been mounted on one surface of a substrate. The lighting drive circuit is electrically connected to the card-type LED illumination source by way of the connector. The card-type LED illumination source preferably includes a metal base substrate and the multiple LEDs that have been mounted on one surface of the metal base substrate. The back surface of the metal base substrate, including no LEDs thereon, thermally contacts with a portion of the illumination apparatus. A feeder terminal to be electrically connected to the connector is provided on the surface of the metal base substrate on which the LEDs are provided.

LED illumination apparatus and card-type LED illumination source

Methods for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs typically on a substrate. Pedestals are deposited on the LEDs with each of the pedestals in electrical contact with one of the LEDs. A coating is formed over the LEDs with the coating burying at least some of the pedestals. The coating is then planarized to expose at least some of the buried pedestals while leaving at least some of said coating on said LEDs. The exposed pedestals can then be contacted such as by wire bonds. The present invention discloses similar methods used for fabricating LED chips having LEDs that are flip-chip bonded on a carrier substrate and for fabricating other semiconductor devices. LED chip wafers and LED chips are also disclosed that are fabricated using the disclosed methods.

Wafer level phosphor coating method and devices fabricated utilizing method

Disclosed is a hybrid integrated circuit device provided with an active filter. The active filter is constructed mainly from a rectifier circuit, a reactor with one terminal connected with an output terminal of the rectifier, a switching element connected with one terminal of the reactor and a smoothing condenser connected with the other terminal of the reactor. The active filter is mounted on an insulating metal substrate and has, other than the above feature, a specific circuit structure wherein the substrate is divided by a ground pattern or power supply pattern into two blocks. One block is for a large current circuit such as the rectifier circuit, the switching element, and a diode and another block for a small signal circuit such as a control circuit. The hybrid integrated circuit device is of remarkably compact size. Also, it is greatly superior in a noise performance because switching noise does not flow into the chassis of electronic equipment from the metal substrate and the control circuit is shielded from the noise produced by the large current circuit, and also because the noise caused by wiring inductance can be limited.

Hybrid integrated circuit device

In a position closest to the mounting position of a microcomputer in a casing of a hybrid integrated circuit device on which is mounted the microcomputer and its peripheral circuit elements, an insertion hole is formed for a non-volatile memory which feeds data to the microcomputer. A socket for connecting the non-volatile memory is provided at the bottom of this insertion hole. Because of this configuration it is possible to connect the microcomputer and the non-volatile memory at an extremely short distance and the mounting efficiency of the integrated circuit device is increased. In addition, the non-volatile memory can detachably be mounted. Furthermore, the external shape of the insertion hole for the non-volatile memory is essentially the same as the external shape of the non-volatile memory so that when the non-volatile memory is inserted, the entire surface of this hybrid integrated circuit device is almost flat, providing excellent handling characteristics.

Hybrid integrated circuit device having a particular casing structure

PURPOSE: To improve a positional accuracy of sheet and to protect thermal dielectric breakdown of a hybrid integrated circuit by temporarily bonding to one main surface of a sub circuit board adhesive resin impregnated sheets having substantially the same shape as this sub circuit board and by regularly bonding the adhesive resin impregnated sheets to a predetermined area on the insulating hard substrate before fixing integrated circuit elements CONSTITUTION: Adhesive resin impregnated sheet 60 is made of Japanese paper impregnated with adhesive resin such as epoxy resin and is laminated onto a sub-circuit board 40 on which a conductive passage 44 or the like is formed into a predetermined pattern and is temporarily bonded by heat treatment to the sub-board 40 When an insulating hard substrate 10 is heated under a predetermined temperature condition with the adhesive resin impregnated sheet 60 under pressure, the impregnated resin of the sheet 60 is again melted and thermally hardened to bond the insulating hard substrate 10 to the sub-board 40 strongly Following this process, on an Ag paste layer 15, chip-like predetermined integrated circuit elements such as the first and second gate arrays 24 and 30, microcomputer 26, and memory 28 are mounted, followed by heating the insulating hard substrate 10 to harden the Ag paste layer 15, thus strongly fixing a predetermined conductive passage 14 obtained by forming integrated circuit elements on the insulating hard substrate 10 COPYRIGHT: (C)1992,JPO&Japio

Masao Kaneko

Papers

Hybrid integrated circuit device

Hybrid integrated circuit device having a particular casing structure

Production of hybrid integrated circuit