A data interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range “serial” type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

High data rate interface apparatus and method

A method for providing client supported features and capabilities to a host in a mobile display digital interface (MDDI) system, the method comprising the steps of adding at least one field to a client capability packet for the client supported features and capabilities; providing values to each field of the at least one field unique to at least one client in the client capability packet; and transmitting the client capability packet from the at least one client to the host as well as a corresponding apparatus.

High data rate interface

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Methods and devices for treating and processing data

A method for a host in a communication system to read from at least one client register in a client, the method comprising the steps of sending a first register access packet by the host to the client comprising a request to read the at least one client register in the client; sending a reverse encapsulation packet by the host to the client; transmitting a second register access packet by the client to the host during a reverse data period of the reverse encapsulation packet; and transmitting register data from the at least one client register within the second register access packet transmitted by the client as well as a corresponding system.

A signal interface for higher data rates

An information-processing apparatus determines whether a stimulation generation unit and a background virtual object contact each other based on position and orientation information about the stimulation generation unit and position and orientation information about the background virtual object. If it is determined that the stimulation generation unit and the background virtual object contact each other, the information-processing apparatus determines whether the stimulation generation unit is included within an attention range. The information-processing apparatus generates operation setting information for controlling an operation of the stimulation generation unit according to a result of the determination and outputs the generated operation setting information to the stimulation generation unit.

Information processing apparatus and information processing method

When a signal indicating a transition state from a synchronized state to an asynchronous state is outputted from a synchronous state register 8, data "0" generated by a "0" generating circuit 20 are stored in a data memory 10 instead of an output of an audio signal generating circuit 6, thus initializing the data memory 10 in advance. In a conventional coded-signal decoding circuit, when a transition was made from a synchronized state to an asynchronous state after failing to establish synchronization, the data memory 10 had to be initialized at a point in time before starting the next synchronous detection, presenting a problem in terms of time. To achieve this, a synchronous control method, a synchronous detecting circuit, and a synchronous detection method are provided.

Coded signal decoding circuit, and synchronous control method for the same, synchronous detecting method, and synchronization detecting circuit therefor

A DA converter includes fs detection means for detecting an input sampling frequency fs of digital data by using a sampling clock LRCK and a master clock xfso, an oversampling digital filter for oversampling the digital data on the basis of the input sampling frequency fs, fs change detection means for detecting a change in the input sampling frequency fs, and mute control means for muting the data to be DA-converted on the basis of the detection result of the fs change detection means.

Digital to analog converter

A clock-supply control system has an AND circuit whereby, when a transfer halt signal and a processing completion signal output by a DSP as well as a transfer halt signal output by a data output unit are all activated, the supply of a clock signal to the DSP is cut off.

Clock-supply control system of digital-signal processors

A class D amplifier defines different sets of resampled points A and B for channels chA and chB of an input digital audio signal, extracts an interpolation signal of the digital audio signal at the resampled points A and another interpolation signal of the digital audio signal at the resampled points B, and makes a correction to the phase of at least one of the interpolation signals. Thereby, radiation noise can be reduced even if the number of channels of the digital audio signal increases.

Signal processing device and class D amplifier that can reduce radiation noise even if the number of channels of a digital audio signal inputted thereto increases

A synchronous control method for a coded signal decoding circuit is disclosed for processing a bit stream consisting of a plurality of successive frames each including sample data of a coded signal to be decoded, and header information having synchronous information indicating a starting position of a frame as a unit of processing and information indicating the frame as a first kind of frame consisting of a relatively small number of sample data per frame or a second kind of frame consisting of a relatively large number of sample data per frame, comprising the steps of: extracting the header information from each frame in said bit stream; detecting whether the state is a synchronized state or an asynchronous state on the basis of the synchronous information included in the extracted header information; judging whether the frame is said first kind or said second kind on the basis of the extracted header information; and performing synchronous control, based on the judgement result on the kind of frame, the synchronous detection result, and the current state, by judging at least whether the next state is a first state indicating an initial state or indicating that the synchronized state has not been detected, a second state indicating that the synchronized state has been detected, a third state indicating that the synchronized state has not been detected in said second state when the contents of said header information indicates the frame is said first kind, or a fourth state indicating that the synchronized state has not been detected in said second state when the contents of said header information indicates the frame is said second kind

Masashi Oki

Papers

Coded signal decoding circuit, and synchronous control method for the same, synchronous detecting method, and synchronization detecting circuit therefor

Digital to analog converter

Clock-supply control system of digital-signal processors

Signal processing device and class D amplifier that can reduce radiation noise even if the number of channels of a digital audio signal inputted thereto increases

MPEG data stream decoder